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About 2,507 papers for “Programmable logic array”
R. Leung, S.M. Lee · 1985
This paper will cover the design of a CMOS EPROM process that serves to implement a 48 P-term AND-OR array with 16 inputs and 8 outputs. The array requires a 20mA quiescent current and 50mA maximum during switching and can be programmed using a conventional 21V EPROM programmer.
Cited by 2
Singla, Pradeep · arXiv (Cornell University) · 2015
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
Cited by 0Open access
R. L. Golden, P. A. Latus, Paul Lowy · IBM Journal of Research and Development · 1980
The Programmable Logic Array (PLA) macro is a physical structure which simplifies LSI chip design while yielding high density and good performance. In addition, the inherent order and regularity of this structure provide opportunities to speed design through automated logic documentation, design verification by computer simulation, and computer-automated physical design. In this paper a chip design methodology is described which is based on the use of PLA structures (or macros) within a chip. Logic functions in array form are specified in a compact notation that is automatically converted either to array personalization patterns or to conventional logic blocks for input to existing checking and testing software. Simulation of any logic array is performed by a single program subroutine operating on these patterns. In addition, the simple, regular nature of the logic array lends itself to automatic generation of the layout geometries necessary to actually build the array on a silicon chip. Programs developed for these purposes and the PLA macro design procedures are described in the context of an engineering design system.
Cited by 13
Singla, Pradeep · Zenodo (CERN European Organization for Nuclear Research) · 2015
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
Cited by 0Open access
MAHSHID TAYARI, Mohammad Eshghi · Journal of Circuits Systems and Computers · 2011
In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.
Cited by 6
P. A. Latus, P. Lowy · 2008
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design while yielding high density and good performance. Zn addition, the inherent order and regularity of this structure provide opportunities to speed design through automated logic documentation, design vergcution by computer simulation, and computer-automated physical design. In this paper a chip design methodology is described which is based on the use of PLA structures (or macros) within a chip. Logic functions in array form are speciJed in a compact notation that is automatically converted either to army personulization patterns or to conventional logic blocks for input to existing checking and testing softwure. Simulation of any logic urray is performed by a single program subroutine operating on these patterns. In addition, the simple, regular nature of the logic array lends itself to automutic generation of the layout geometries necessary to actually build the array on a silicon chip. Progrums developedfor these purposes and the PLA mucro design procedures are described in the context of an engineering design system.
Cited by 0
Edward Karalis · 1978
Cited by 0
2008
Programmable Logic Array (PLA) adders are described which petform an addition in one cycle with a single pass through a PLA and require a reasonable number ofproduct terms for 8-, an 16-, or even a 32-bit adder. The PLA features two-bit input decoders feeding an AND array followed by an OR array whose outputs are pairwise Exclusive-oRed. Carrylook-ahead adder equations, adapted to the PLA to require relatively few product terms, are adjusted for maximum sharing ofproduct terms. The number of unique product terms is a relative measure of one of the physical dimensions of the PLA. Equations for contiguous sum bits are grouped into strings, each using a common input carry. A procedure optimally assigns sum bits to strings to further minimize the total number of unique product terms. The methods are extended to PLAs with decoders of increased inputs and substantially reduced product terms. They can serve as dedicated macro functions on a chip, using special decoders relevant to adders. As a result, the other PLA dimension comprising the number of outputs from all input decoders increases only moderately, and can even decrease, with larger decoders. Finally, the PLA adder can be further substuntially compressed by splitting the OR array into two parts such that a row of the AND array is shared between two product terms, and OR an array column is shared between two sums of product terms.
Cited by 0
Gilbert Bernard Nebgen · OakTrust (Texas A&M University Libraries) · 1975
Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.
Cited by 0
Yao Li, Andrew A. Kostrzewski, Dai Hyun Kim et al. · Optics Letters · 1988
A new method to realize a medium-scale, free-space optical programmable logic array is proposed. By using either a two-dimensional optical spatial light modulator or an array of one-dimensional spatial light modulators inside a lens-based multiple-beam-path cavity, an array of optical multiple-variable logic product terms is generated. This device, together with a programmable multiple-variable OR matrix, can be used to implement any Boolean combinatorial logic operations. For an optical binary combinatorial logic computation, the proposed method efficiently uses three-dimensional space and optical elements. Preliminary experimental results obtained using an inexpensive liquid-crystal television are included.
Cited by 7
Sumner I · Science and Technology Facilities Council
Cited by 0Open access
Pradeep Singla · Zenodo (CERN European Organization for Nuclear Research) · 2015
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
Cited by 0Open access
Dhruv M. Patel, Jignesh Bhatt, Sanjay Trivedi · ISA Transactions · 2014
Cited by 15
Gaddourah, Mousa Isa · Research Publication Repository of King Fahd University of Petroleum and Minerals (King Fahd University of Petroleum and Minerals) · 1980
Cited by 0
Andrew C. Ling · 2005
Field-Programmable gate arrays (FPGAs) are reprogrammable logic chips that can be config-ured to implement various digital circuits. FPGAs are fast replacing custom ASICs in many areas due to their flexibility and fast turn around times for product development. However, these benefits come at a heavy cost of area, speed, and power. The FPGA architecture and technology mapping phase are fundamental in determining the performance of the FPGA. This thesis presents novel tools using Boolean satisfiability (SAT) to aid in both these areas. First, an architecture efficiency evaluation tool is developed. The tool works by reading in a description of the FPGA architecture and rates how flexible that architecture can be in implementing various circuits. Next, a novel technology mapping approach is developed and compared to current methods. This work contrasts with current approaches since it can be applied to almost any FPGA architecture. Finally, a resynthesis algorithm is described which rates the utility of current FPGA technology mappers where it can also be used to discover optimal configurations of common subcircuits to digital design.
Cited by 0
Niranjan Kulkarni, Jinghua Yang, Sarma Vrudhula · 2014
Threshold-logic gates have long been known to result in more compact and faster circuits when compared to conventional AND/OR logic equivalents [1], However, threshold logic based design has not entered the mainstream design technology (neither custom ASIC nor FPGA) due to the lack of efficient and reliable gate implementations and the necessary infrastructure for automated synthesis and physical design. This paper is a step toward addressing this gap. We present the architecture of a novel programmable logic array, referred to as Field Programmable Threshold-Logic Array (FPTLA), in which the basic cells are differential mode threshold-logic gates (DTGs). Each individual DTG cell is a clock edge-triggered circuit that computes a threshold-logic function. A DTG can be programmed to implement different threshold logic functions by routing appropriate signals to their inputs. This reduces the number of SRAMs inside the logic blocks by about 60% compared to conventional CLBs, without adding any significant overhead in the routing infrastructure. Since a DTG is essentially a multi-input, edge-triggered flipflop that computes a threshold function, a network of DTGs forms a nano-pipelined circuit. The advantages of such a network are demonstrated on a set of deeply pipelined datapath circuits implemented on FPTLAs and conventional FPGAs using the well established FPGA design framework VTR (Verilog To Routing) and VPR (Versatile Place and Route) [2]. The results indicate that an FPTLA can achieve up to 2X improvement in delay for nearly the same energy and logic area compared to the conventional LUT based FPGA. Although differential mode circuits can potentially be more sensitive to process variations, FPTLAs can be made robust to such variations without sacrificing their improved energy efficiency and performance over FPGAs.
Cited by 4
J. A. Lockwood · The electrical engineering handbook/Electrical engineering handbook series/Electrical engineering handbook · 1999
Cited by 0
K. C. WEI, Jinn-Jong Sheu, B. D. LIU · International Journal of Electronics · 1994
Abstract A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.
Cited by 0
Sangwook Youn (17715824), Jungjin Lee (10338428), Sungjoon Kim (2123797) et al. · Figshare · 2024
In\nthis study, we demonstrate the implementation of programmable\nthreshold logics using a 32 × 32 memristor crossbar array. Thanks\nto forming-free characteristics obtained by the annealing process,\nits accurate programming characteristics are presented by a 256-level\ngrayscale image. By simultaneous subtraction between weighted sum\nand threshold values with a differential pair in an opposite way,\n3-input and 4-input Boolean logics are implemented in the crossbar\nwithout additional reference bias. Also, we verify a full-adder circuit\nand analyze its fidelity, depending on the device programming accuracy.\nLastly, we successfully implement a 4-bit ripple carry adder in the\ncrossbar and achieve reliable operations by read-based logic operations.\nCompared to stateful logic driven by device switching, a 4-bit ripple\ncarry adder on a memristor crossbar array can perform more reliably\nin fewer steps thanks to its read-based parallel logic operation.
Cited by 0Open access
Novikov, P. E., Korsak, K. V. · Репозиторий БГУИР (BSUIR Repository) · 2023
The article deals with the basic architecture of programmable logic integrated circuits and basic logic element, part of its main component - configurable logic block. Electrical functional circuit of the basic logic element with the ability to perform the sum operation was designed. On the basis of the functional diagram the RTL-representation of the basic logic element was obtained and the results of its modeling are presented.
Cited by 0Open access