David Barina, Pavel Zemčík · 2013
With the start of the widespread use of discrete wavelet transform the need for its efficient implementation is becoming increasingly more important. This work presents a general approach of discrete wavelet transform scheme vectorisation evaluated on an FPGAbased Application-Specific Vector Processor (ASVP). This unit can be classified as SIMD computer in Flynn’s taxonomy. The presented approach is compared with two other non-vectorised approaches. Using the frequently exploited CDF 9/7 wavelet, the achieved speedup is about 2:6 compared to naive implementation.
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B Rajeshwari, V Lasya, T Sourabh et al. · 2024
This work presents a vector processor architecture which can perform faster convolutions at the edge node compared to cloud computations. The proposed vector processor has an automated CNN Unit that performs convolution and max pooling functions. In addition to this, the processor is also capable of carrying out scalar and vector operations like addition and multiplication based on custom instructions. The processor can perform faster multiplications owing to a custom Dadda multiplier design which is 2.12 times faster than the traditional Dadda multiplier. The convolutor is parallelized and pipelined achieving a 5.405 speedup over the regular convolutor. The proposed processor is ultimately 97,888 times faster than Google Colab for convolution and max pooling.
Cited by 1
Taku Ya Iwahashi, Takehide Shi Ba Yama, Masanori Hashimoto et al. · 2000
A vector quantization processor suitable for video communication has been developed. It performs 10 frames/sec of encoding and decoding QCIF with the FRMSHVQ algorithm. It consumes 49mW at 25MHz. The chip is fabricated in a 0.35pm CMOS technology. I.
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Gee, Jeffrey D, Author, Smith, Alan Jay, Author · UC Berkeley
Cache memories have not been used for vector supercomputers, as far as we know, because of a belief that program behavior in relevant workloads was such as to preclude efficient cache operation. It has been possible to make efficient use of such machines by carefully programming around the resulting long memory delays, although unmodified, "dusty-deck" code usually performs poorly. In related research, we have found that hit ratios are high for large caches in processors with vector workloads. In this paper, we address the specific issue of the direct effect of cache memory on vector processor performance. <p>The issue in processor design is machine performance, of which the hit ratio of the cache is only one determinant. In this paper, we simulate three vector processors, the designs for which are derived from expected technology changes applied to the Ardent Titan. Our simulator is an accurate timing model incorporating the necessary aspects of the design of the cache and memory system. We find that current trends in memory and processor performance will lead to increasingly severe memory speed and bandwidth limitations. Either of two designs using large cache memories (2MB, 4MB) on the average double processor performance relative ot the design without a cache. Hit ratios for almost all of the programs used for trace driven simulation, drawn from real Ardent workloads, are over 99%. Based on the work presented here and elsewhere, we recommend that future supercomputers incorporate cache memories
Cited by 1
Dang Nur Engin, B. L. Dang Ýý, Nur Engin Ý et al. · 2007
This paper describes the mapping of Finite Impulse Response (FIR) and Decimation filters on a new DSP architecture: the Co-Vector Processor (CVP) developed by Philips. This architecture is targeting the baseband signal processing algorithms for the third generation mobile communication (3G). CVP is a Very Long Instruction Word (VLIW) architecture with functional units supporting vector parallelism. To exploit efficiently the architecture, a large portion of the targeted DSP algorithms must be properly vectorized. In this paper, different vectorization strategies for FIR and Decimation filters for the CVP architecture are investigated. The approach used is to restructure the original sequential algorithms into block forms that are suitable for parallel processing. In addition, the vectorization should fully utilize the Multiply-Accumulate (MAC) structure. It is shown that for the targeted filters, several good vectorization strategies can be applied. The benchmark results obtained using the proposed strategies outperform results of other architectures previously reported.
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Manikandan Narayanan · 1994
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Joseph Gebis, Sam Williams · 2004
Processors for mobile multimedia devices must be low power while having excellent performance on media applications. Our processor, VIRAM1, accomplishes this by combining vector processing with embedded DRAM. VIRAM1 includes a scalar core, 13 megabytes (104 megabits) of DRAM, and four vector datapaths. It consumes 2 watts at 200 MHz and executes up to 9.6 giga-ops (16 bit) per second. 1.
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Silviu Chiricescu, S.M. Chai, K. Moat et al. · 2005
A large number of sensors (i.e., video, radar, laser, ultrasound, etc.) that continuously monitor the environment are finding their way in the average automobile. The algorithms processing the data captured by these sensors are streaming in nature and require a high rate of computation. Due to the characteristics of the automotive environment, this computation has to be delivered under very low energy and cost budgets. The reconfigurable streaming vector processing (RSVP/spl trade/) architecture is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture and its second implementation, RSVP II. Our results show significant speedups on data streaming functions running compiled code. On a lane tracking application, RSVP II shows impressive performance results. From a performance/$ and performance/mW perspective, RSVP architecture compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.
Cited by 11
Abel Palaty, Mohammad Suaib, Kumar Sambhav Pandey · Communications in computer and information science · 2011
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Ivan Chak · Library and Archives Canada (Government of Canada) · 2013
VecTor is a suite of computer programs developed for the nonlinear finite element analysis of reinforced concrete structures. Due to the substantial nature of output data produced by the programs, accessing pertinent analysis information is not easily accomplished. A graphics-based post-processor would greatly improve the overall utility of the VecTor programs by allowing the multitude of information to be visually displayed and manipulated for the purposes of data synthesis and rapid verification of results.\n\nThe intent of this manual is to demonstrate a post-processor program which reads and displays the results of VecTor-based analyses in a robust and straightforward manner. The proposed post-processor program, named Janus, will provide the user with the capability to display both local and global response characteristics. Janus will allow the user to comprehensively recall and manipulate structural analysis results on a model-wide basis as well as display pertinent information for individually specified elements of interest.
Cited by 4
K. Karagianni, T. Stouraitis · 2002
A parallel VLSI architecture for the computationally efficient implementation of the elementary 3-D geometrical transformations is introduced. The trivial entries in the elementary transformation matrices are exploited, so that the matrix-matrix products required for the Transformation Matrix computation, are replaced by corresponding operations of the complexity of a vector operation. Acceleration of 68% to 84% per elementary transformation is achieved, at minimal hardware cost.
Cited by 3
Nikolay Dikarev, B. M. Shabanov, Aleksandr Shmelëv · Program systems theory and applications · 2017
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Cited by 0Open access
Eugene P. Mosca, Frank P. Pursel, Daniel Griffin et al. · 1989
Abstract : An Acousto-Optic Technique is used to design and construct a prototype of a processor capable of multiplying a 128 x 128 element matrix by a 128 element vector. The elements of the matrix and the vectors are complex numbers. The device is specified to execute 100,000 vector/matrix products per second with 8-bit accuracy. The performance of each component of the prototype was evaluated as was the impact of component performance on system performance. Keywords: Acousto optical; Vector matrix product; Diode laser; Optical processing.
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Rostislav S. Starikov · Journal of Communications Technology and Electronics · 2008
Results of the analysis of realistic architectures of optoelectronic vector-matrix processors are presented. Estimates of the attainable speed and accuracy of calculations, as well as estimates of the required volumes of preprocessing and postprocessing of input and output data, are made.
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Nikolay Dikarev, B. M. Shabanov, Aleksandr Shmelëv · Program systems theory and applications · 2015
Н. И. Дикарев, Б
Cited by 1Open access
F. Okamoto, Yoshihisa Hagihara, C. Ohkubo et al. · 1991
High-speed vector processing for matrix calculations is important to the handling of various scientific computations and is an operation method in which the same operations are continuously carried out with the issue of only a single instruction. In response to the need for high-speed vector processing, this vector-pipelined-processor (VPP) uses parallel pipeline operation to reach 200MFLOPS and 500MOPS at a 100MHz clock cycle. Construction of a 1-GFLOPS supercomputer requires only 5 VPP ULSis.
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F. Hertweck, M. Feilmeier, J. Joubert et al. · MPG.PuRe (Max Planck Society) · 1984
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位守 弘充, 中村 宏, 朴 泰祐 et al. · Terrestrial Environment Research Center (University of Tsukuba) · 1993
journal article
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F. Jutand, N. Demassieux, D. Vicard · 2005
Vector quantization and Dynamic Pattern Matching are basic operations to achieve continuous speech recognition. Only their implementation in VLSI circuits could provide the high performance required by real-time computation and allow the design of low-cost systems, two key points for the industrial development of continuous speech recognition. Using an Integrated "Design" Methodology, we have combined optimizations at the algorithmic, architectural and layout levels, to design a high throughput Vector Distance Processor, and a set of matched complementary cells, that allows an easy implementation of various Vector Quantization and Dynamic Pattern Matching chips. As an application, we have designed a low-cost VLSI circuit achieving diphone spotting. This single chip implements a Dynamic Pattern Matching algorithm for 20-frame patterns and provides every 10ms the four best candidates among 500 patterns.
Cited by 2
Silvia Melitta Mueller, Christian Jacobi, Hwa-Joon Oh et al. · 2005
The floating-point unit in the synergistic processor element of the 1st generation multi-core CELL processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low latency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graphics. The FPU has 3 different latencies, optimizing the performance critical single precision FMA operations, which are executed with a 6-cycle latency at an 11FO4 cycle time. The latency includes the global forwarding of the result. These challenging performance, power, and area goals were achieved through the co-design of architecture and implementation with optimizations at all levels of the design. This paper focuses on the logical and algorithmic aspects of the FPU we developed, to achieve these goals.
Cited by 52