Predicting HPC parallel program performance based on LLVM compiler
Weizhe Zhang, Meng Hao, Marc Snir · Cluster Computing · 2016
Cited by 17
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About 7,644 papers for “parallel program performance”
Weizhe Zhang, Meng Hao, Marc Snir · Cluster Computing · 2016
Cited by 17
Yufeng Liu, Yunlan Wang, Tianhai Zhao et al. · SSRN Electronic Journal · 2023
Cited by 0Open access
Yunlan Wang, Yufeng Liu, Rui Zhang et al. · Computer Physics Communications · 2024
Cited by 3
Kuan Ching Li · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2001
Processamento distribuído tem sido utilizado amplamente para melhorar o desempenho de aplicações com alta demanda computacional. Diferentes arquiteturas e topologias distribuídas têm sido pesquisadas e utilizadas para prover o alto desempenho, proporcionando assim o recurso necessário para a exploração do paralelismo presente nas aplicações. A facilidade para construir sistemas computacionais de alto desempenho a partir de estações de trabalho interligadas através de redes de alta velocidade, aliada ao custo relativamente baixo e ao crescente avanço da tecnologia de circuitos integrados, possibilita a montagem de redes de computadores de baixo custo para a execução de aplicações paralelas. Devido a este fato, diversos sistemas de software para redes de estações têm sido desenvolvidos, visando a integração dos componentes distribuídos para a agregação das suas capacidades de processamento. No entanto, o processo de desenvolvimento de aplicações é complexo e difícil, dado que são necessários identificar o paralelismo existente nestas aplicações, e providenciar as comunicações necessárias. Neste trabalho, é apresentada uma proposta de metodologia de análise e predição de desempenho de programas paralelos, implementados com interface de passagem de mensagem (MPI), em ambientes de redes de estações de trabalho. É definida neste trabalho uma extensão da classe de grafos de tempo T-graph, denominado T-graph*, que representa, em alto nível, os programas paralelos instrumentados com MPI no nível de grafos. Com a construção de um grafo nesta classe, é possível conhecer o fluxo da execução do programa, do ponto de vista algorítmico. Ainda, é definida uma outra classe de grafos, denominada DP*Graph, que representa os programas paralelos com alto grau de detalhes, como mostrar de forma clara pontos de ocorrência de comunicação entre os nós de processamento do sistema computacional. Em paralelo com recursos e técnicas de modelagem analítica, são definidas estratégias para a avaliação de desempenho dos sistemas computacionais envolvidos. Uma vez obtidas as representações em grafos do programa paralelo e junto com as modelagens já refinadas e definidas, é possível efetuar avaliações necessárias e obter assim predições de desempenho, baseadas em dados experimentais obtidos previamente. Finalmente, os resultados experimentais obtidos mostram a viabilidade da metodologia definida nesta proposta, tanto a sua utilização e quanto à coerência das estratégias aplicadas neste trabalho.
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久保田 和人, 板倉 憲一, 佐藤 三久 et al. · Terrestrial Environment Research Center (University of Tsukuba) · 1999
journal article
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Cohen Garrett And, W. E. Cohen, W. D. Garrett et al. · 2007
The ULTRA (UAH Logging, Trace Recording, and Analysis) instrumentation system provides an accurate and low-cost means of collecting traces of Message Passing Interface (MPI) program execution. These traces preserve the original parallel program's data-dependencies by recording each MPI operation performed; the message source, destination, and size; and the number of application instructions preceding the operation. Using these traces enables low-cost simulations for determining the performance of various node and communication hardware combinations although the cluster used to collect the data and the cluster being simulated differ significantly.
Cited by 0
Naim, O, Hey, A J G, Zaluska, EJ · ePrints Soton (University of Southampton) · 1996
Performance is a critical issue in current massively parallel processors. However, delivery of adequate performance is not automatic and performance evaluation tools are required in order to help the programmer to understand the behaviour of a parallel program. In recent years, a wide variety of tools have been developed for this purpose, including tools for monitoring and evaluating performance and viaualization tools. However, these tools do not provide an abstract representation of performance. Massively parallel processors can generate a huge amount of performance data, and sophisticated methods for representing and displaying these data (e.g. visual and aural) are required. Performance views are not scalable in general and do not represent an abstraction of the performance data.<br/><br/>The do-loop-surface display is proposed as an abstract representation of the performance of a particular do-loop in a program. It has been used to improve the performance of a matrix multiply parallel algorithm as well as to understand the behaviour of the following applications: matrix transposition (TRANS1) and fast Fourier transform (FFT1) from the Genesis benchmarks, and the kernel of a fluid dynamics package (FIRE). These experiments were performed on a CM-5, a Meiko CS-1 and a PARSYS Supernode. The examples demonstrate that the do-loop-surface display is a useful way to represent performance. It is implemented using AVS (application visualization system), a standard data visualization package.<br/>
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Jiaxin Liu, Xinglai Ji · 2024
The LeaderRank algorithm identifies influential nodes using the idea of the random walk and performs well in the identification of hub genes in biological networks. The rapid development of biological technologies promotes the evolution of networks to be highly complex and increasing largely in size. In this study, we introduce LRCu, for computing LeaderRank using CUDA, to identify hub genes. The results show that the parallel implementation is highly effective and achieves a speedup of more than 42 times for a 13,000-gene network, thereby enhancing large-scale network computation.
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2008
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Michel Pahud, Frédéric Guidec, Thierry Cornu · INRIA a CCSD electronic archive server · 1997
Cited by 0Open access
Jerzy Krawiec · Prace Naukowe Akademii im Jana Długosza w Częstochowie Technika Informatyka Inżynieria Bezpieczeństwa · 2017
Cited by 0
Lawrence J. Tenny, Lawrence J. Tenny · 1992
Writing good programs for high performance parallel computers is difficult. The programmer must have a deep understanding of the underlying machine architecture. Issues such as memory hierarchy, communication topology, processor architecture, task scheduling, and processor allocation, can have a dramatic effect on a program&apos;s performance. What makes matters difficult is that, if peak performance is to be achieved, radical architectural differences require the program to be customized for each machine. Source to source program restructuring offers the opportunity for a single incarnation of a program to be transformed at the source level so that it better matches capabilities of any given parallel computer. For serial machines, well-known compiler optimization techniques are sufficient. For parallel machines, however, the issue is not so clear. Fundamental architectural differences considerably complicate the process of improving the program-machine match. No longer does a relatively si...
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Vikram Adve, Rizos Sakellariou · 2000
Syntax Tree (AST). STG nodes are created as appropriate statements are encountered in the AST. Thus, program statements, such as DO, IF, CALL, PROGRAM/FUNCTION/SUBROUTINE, STOP/RETURN, trigger the creation of a single node in the graph; encountering one of the rst two also leads to the creation of an enddo-node or an endif-node, a then-node and an else-node, respectively. Any contiguous sequence of other computation statements that are executed by the same set of processors are grouped into a single computational task (contiguous implies that they are not interrupted by any of the above statements or by communication). Identifying statements that are computed by the same set of processors is a critical aspect of the above step. This information is derived from the computation partitioning phase of the compiler and is translated into a symbolic integer set [1] that is included with each task. By having a general representation of the set of processors associated with each task, our re...
Cited by 0
Vikram Advea, Rizos Sakellariou · Lecture notes in computer science · 2001
Cited by 22
Michel Pahud, Frédéric Guidec, Thierry Cornu · Lecture notes in computer science · 1997
Cited by 2
R. Bruce Irvin, Barton P. Miller · 1996
Programs written inhigh-level parallel languages need profiling tools that provide performance data in terms of the semantics of the high-level language. But high-level performance data can be incomplete when the cause of a performance problem camot be explained in terms of the semantics of the language. We also need the ability to view the performance of the underlying mechanisms used by the language and correlate the underlying activity to the language source code. The key techniques for providing these performance views is the ability to map low-level performance data up to the language abstractions. We describe how we use this information to produce performance data at the higher levels, and how we present this data in terms of both the code and parallel data structures.
Cited by 15Open access
Anjiang Wei, Allen Nie, Thiago Teixeira et al. · arXiv (Cornell University) · 2024
Modern scientific discovery increasingly relies on high-performance computing for complex modeling and simulation. A key challenge in improving parallel program performance is efficiently mapping tasks to processors and data to memory, a process dictated by intricate, low-level system code known as mappers. Developing high-performance mappers demands days of manual tuning, posing a significant barrier for domain scientists without systems expertise. We introduce a framework that automates mapper development with generative optimization, leveraging richer feedback beyond scalar performance metrics. Our approach features the Agent-System Interface, which includes a Domain-Specific Language (DSL) to abstract away the low-level complexity of system code and define a structured search space, as well as AutoGuide, a mechanism that interprets raw execution output into actionable feedback. Unlike traditional reinforcement learning methods such as OpenTuner, which rely solely on scalar feedback, our method finds superior mappers in far fewer iterations. With just 10 iterations, it outperforms OpenTuner even after 1000 iterations, achieving 3.8X faster performance. Our approach finds mappers that surpass expert-written mappers by up to 1.34X speedup across nine benchmarks while reducing tuning time from days to minutes.
Cited by 0Open access
LeBlanc, Thomas J., Markatos, Evangelos P. · UR Research (University of Rochester)
The last decade has produced enormous improvements in processor speeds without a corresponding improvement in bus or interconnection network speeds. As a result, the relative costs of communication and computation in shared-memory multiprocessors have changed dramatically. An important consequence of this trend is that many parallel applications, which depend on a delicate balance between the cost of communication and computation, do not execute efficiently on today's shared-memory multiprocessors. In this paper we quantify the effect of this trend in multiprocessor architecture on parallel program performance. Our experiments on bus-based, cache-coherent machines like the Sequent Symmetry, and large-scale distributed-memory machines like the BBN Butterfly, demonstrate that applications scale much better on previous-generation machines than on current machines. In addition, we show that some scalable machines support fine-grain, shared-memory programs better than some bus-based, cache-coherent machines, without significantly greater programming effort. From our experiments we conclude that communication has become a dominant source of inefficiency in shared-memory multiprocessors, with serious consequences for system software involved in scheduling and decomposition decisions. In particular, we argue that shared-memory programming models that could be implemented efficiently on the machines of yesterday do not readily port to state-of-the-art machines, and that current software trends in support of fine-grain parallel programming are at odds with hardware trends.
Cited by 0
Nicola Mazzocca, Massimiliano Rak, Umberto Villano · Lecture notes in computer science · 2001
Cited by 19
Ronald Brian Brightwell · 1994
evaluation of the effectiveness of the Maximum Benefit metric. ii ACKNOWLEDGEMENTS First, I would like to extend sincere thanks and appreciation to Dr. Donna Reese and Dr. Cedell Alexander for their part in this research. I am grateful to Dr. Reese for giving me the opportunity to work for her, and I am thankful for her patience and guidance. I am indebted to Dr. Alexander both for the willingness to share his research efforts and for the direction he has given to mine. Secondly, I would like to thank Dr. Susan Bridges and Dr. Rainey Little for their time and efforts as members of my graduate committee. Finally, I would like to thank the members of the System Software thrust at the MSU/NSF Engineering Research Center and the members of the Computer Science department faculty in general for all of the knowledge that they have passed on to me. iii TABLE OF CONTENTS Page ACKNOWLEDGEMENTS ii .............................................. LIST OF TABLES vi .............................
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