Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 10,000 papers for “Bit array”

Three-Bit DMTL Phase Shifter for Phased Array Antennas

N. M. Mary Sindhuja, S. Kanthamani · Journal of Circuits Systems and Computers · 2018

RF MEMS phase shifter is a device that is used to modify the transmission phase of RF signal and provide signal control. Phase shifters are high-value components used in phased array antenna architectures. In phased array antenna the phase shifter is used to provide reliable electronic beam steering. The proposed 3-bit distributed MEMS transmission line (DMTL) phase shifter is designed using elevated coplanar waveguide (ECPW) transmission line for the first time, which results in better return loss of [Formula: see text]14.23[Formula: see text]dB and an average insertion loss of [Formula: see text]1.46[Formula: see text]dB. This paper discusses the development of ECPW-based 3-bit DMTL phase shifter designed to operate at 15[Formula: see text]GHz.

Cited by 6

Asymptotic Signal Detection Rates with 1-Bit Array Measurements

Manuel Stein · arXiv (Cornell University) · 2018

This work considers detecting the presence of a band-limited random radio source using an antenna array featuring a low-complexity digitization process with single-bit output resolution. In contrast to high-resolution analog-to-digital conversion, such a direct transformation of the analog radio measurements to a binary representation can be implemented hardware and energy-efficient. However, the probabilistic model of the binary receive data becomes challenging. Therefore, we first consider the Neyman-Pearson test within generic exponential families and derive the associated analytic detection rate expressions. Then we use a specific replacement model for the binary likelihood and study the achievable detection performance with 1-bit radio array measurements. As an application, we explore the capability of a low-complexity GPS spectrum monitoring system with different numbers of antennas and different observation intervals. Results show that with a moderate amount of binary sensors it is possible to reliably perform the monitoring task.

Cited by 0Open access

A systematic approach to bit recursive systolic array design

K.R. Liu, K. Yao · 2003

This approach provides a systematic way to design a recursive computational architecture instead of a bit-slice architecture. Since the relationship is much stronger at the bit level than at the work level and most relations can be described as shift-and-operate computations, these kinds of relations can be formulated as recursive equations, from which the systolic array can be built without deriving the dependence graph of the bit-level computation. Some design examples for bit-recursive systolic array presented: multiplier, inner product and convolution correlation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 2

Design and Implementation of Four Bit Binary Array Multiplier

Yasmeen Saundatti · International Journal of Scientific Engineering and Research · 2016

Recently, several experimental systems based on programmable logic have been designed and implemented which are programmed using a hardware design methodology.One necessary component of the software environment will be a library of standard macro cells corresponding to commonly used arithmetic and logical operations.In this paper Array multiplier is designed especially for programmable logic.This multiplier is cellular, highly pipelined and uses only of local interconnections.The design is particularly carried out for a 4-bit multiplier.

Cited by 0Open access

Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme

Kyung-Saeng Kim, Kwang Myoung Rho, Kwyro Lee · 2002

An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring.

Cited by 0

A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio

Xiaojin Zhao, Peizhou Gan, Qiang Zhao et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2019

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of 3.23 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (i.e. 764 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF's uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips' reliability under varied operating temperature from -40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by 1.16~4.29×, with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

Cited by 31

Gridless Channel Estimation for Mixed One-Bit Antenna Array Systems

Chang-Jen Wang, Chao-Kai Wen, Shi Jin et al. · IEEE Transactions on Wireless Communications · 2018

A receiver architecture with low-resolution analog-to-digital converters (ADCs) coupled with large antenna arrays has drawn considerable interest in the millimeter wave (mm-wave) system. Although architecture with pure one-bit ADCs has low power cost, such a system presents many challenges for synchronization, channel estimation, and power level estimation. Research has been conducted recently on the so-called mixed one-bit system, in which most antennas are equipped with one-bit ADCs, and a few have high-resolution ADCs. Despite the advantages of this system, studies on how to efficiently use high-resolution outputs to aid the one-bit system are lacking. This research considers the channel estimation problem to fill this gap and proposes a two-step channel estimator by utilizing the different features of mixed outputs. The channel gain can be extracted from high-resolution ADCs, and the channel angle can be extracted by the combination of additional one-bit ADCs. The proposed estimator leverages the sparsity feature of the channel in mm-wave. In contrast to previous works that used compressive sensing techniques, which confine the estimate to the set of grid angle points and induce estimation bias, the proposed estimator is gridless and treats the angle as a continuous parameter. The simulation results demonstrate that the proposed method yields significantly lower mean square errors than the conventional maximum likelihood estimator. In addition, this paper investigates ways to further improve the channel estimate by arranging the locations of high-resolution ADCs. Several useful observations on system design are obtained through our analysis.

Cited by 29

CMOS latch bit-cell array for low-power SRAM design

Yeonbae Chung, Weijie Cheng · IEICE Electronics Express · 2010

The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and write methods that result in low operating power dissipation in the nature. A 1.8V SRAM test chip has been fabricated in a 0.18µm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the standard 6T SRAM.

Cited by 2Open access

DoA Estimation Using Low-Resolution Multi-Bit Sparse Array Measurements

Saeid Sedighi, Mallikarjun Shankar, Mojtaba Soltanalian et al. · IEEE Signal Processing Letters · 2021

This letter studies the problem of Direction of Arrival (DoA) estimation from low-resolution few-bit quantized data collected by Sparse Linear Array (SLA). In such cases, contrary to the one-bit quantization case, the well known arcsine law cannot be employed to estimate the covaraince matrix of unquantized array data. Instead, we develop a novel optimization-based framework for retrieving the covaraince matrix of unquantized array data from low-resolution few-bit measurements. The MUSIC algorithm is then applied to an augmented version of the recovered covariance matrix to find the source DoAs. The simulation results show that increasing the sampling resolution to 2 or 4 bits per samples could significantly increase the DoA estimation performance compared to the one-bit sampling regime while the power consumption and implementation costs is still much lower in comparison to the high-resolution sampling implementations.

Cited by 25Open access

One-bit Error-Feedback Quantizer for Uniform Linear Antenna Array

Shûichi Ohno, Shenjian Wang · 2021 29th European Signal Processing Conference (EUSIPCO) · 2021

One-bit error-feedback quantizers for uniform linear antenna arrays are developed to enable efficient spatial noise shaping. The SNR of the maximum ratio combiner for received signals quantized by one-bit error-feedback quantizers is evaluated. Then, the optimal error-feedback quantizer that maximizes the worst SNR for the signals whose arrival angles are in a fixed range of interest is designed. Numerical results are provided to show that our one-bit spatial noise shaping exhibits flat BER performance for the signals from the prescribed range.

Cited by 1

Fabrication of 1K-Bit 1T2C-Type Ferroelectric Memory Cell Array

Shuu’ichirou Yamamoto, Toru Ishikawa, Takaaki Fuchikami et al. · Integrated ferroelectrics · 2004

A 1K-bit 1T2C-type ferroelectric memory array has been designed and fabricated by combination of a 0.35 μm gate length CMOS process and a 3 μm design rule ferroelectric process. The write and readout operation in a 1K-bit 1T2C-type memory array cell has been confirmed experimentally.

Cited by 0

A 27 GHz, simple 2-bit 1×8 phased array

Jun-Xian Liu, Yunying Man, Hao Yang et al. · Journal of Electronic Science and Technology · 2024

This study demonstrates a simple 2-bit phased array operating at 27 ​GHz that supports one-dimensional beam scanning with left-handed circular polarization (LHCP). The antenna is constructed using a compact four-layer printed circuit board (PCB) structure, consisting of a 90° phase shifter layer with microstrip structures, a ground (GND) layer, a direct current (DC) control layer, and a circularly polarized annular radiation patch layer with 1-bit phase shifting. Based on the proposed unit structure, a 1×8 array with half-wavelength inter-element spacing was designed and validated. Experimental results show that the array achieves a peak gain of 10.23 dBi and is capable of beam scanning within ±50°.

Cited by 2Open access

A fault-tolerant bit-serial array structure for digital filters

Rajkumar Roy, Magdy Bayoumi · 2003

The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are used on the cell level which increases the throughput of the proposed pipelined structure. Moreover, the proposed architecture has distributed error-control features. The necessity of such distributed fault-tolerance in DSP (digital signal processing) architectures is due to its susceptibility to permanent and intermittent errors caused by the high complexity of these circuit structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 3

Reconfigurable One-Bit Millimeter-Wave Array with Compact Feeding Network

R. Yao, Yan Wang · 2023

A low cost 1-bit reconfigurable beam steering $1\times 4$ antenna array for mobile terminals is investigated in this paper. The overlapped −10dB impedance bandwidth of 26.6-28.4 GHz is achieved. With an element spacing of $0.5\lambda$, the beam-steering range of this array can reach-56.5° to 49.5° by steering the beam to 5 different angles of 0°, ±20°, ±40°. The 1-bit phase shifting is realized by combination of ON-OFF states of switches on the feeding network. Curved microstrip feedline is used to mitigate the quantization error of the 1-bit phase. To get a more miniaturized array, a compact feeding network is constructed. The proposed array has a compact size and low cost which are practical properties in applications on mobile terminals.

Cited by 1

A high-speed 8*8-bit CMOS parallel array processor

K.-K. Lee, R.G. Deshmukh · 2003

The authors present an architecture for an 8-b*8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 0