Matteo Varvello, Rafael Laufer, Feixiong Zhang et al. · IEEE/ACM Transactions on Networking · 2015
The rapid growth of server virtualization has ignited a wide adoption of software-based virtual switches, with significant interest in speeding up their performance. In a similar trend, software-defined networking (SDN), with its strong reliance on rule-based flow classification, has also created renewed interest in multi-dimensional packet classification. However, despite these recent advances, the performance of current software-based packet classifiers is still limited, mostly by the low parallelism of general-purpose CPUs. In this paper, we explore how to accelerate packet classification using the high parallelism and latency-hiding capabilities of graphic processing units (GPUs). We implement GPU-accelerated versions for both linear and tuple search, currently deployed in virtual switches, and also introduce a novel algorithm called Bloom search. These algorithms are integrated with high-speed packet I/O to build GSwitch, a GPU-accelerated software switch, and also to extend Open vSwitch. Our experimental evaluation indicates that, under realistic rule sets, GSwitch is at least 7 × faster than an equally-priced CPU classifier. We also show that our GPU-accelerated Open vSwitch outperforms the classic Open vSwitch implementation by a factor of 10, on average.
Cited by 50
J. Dowling, John Welling, Loral AeroSys et al. · UA Campus Repository (The University of Arizona) · 1995
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada
Cited by 0
Torsten Meyer, Daniel Raumer, Florian Wohlfart et al. · 2014
Commodity hardware can be used to build a software router that is capable of high-speed packet processing while being programmable and extensible. Therefore, software routers provide a cost-efficient alternative to expensive, special hardware routers. The efficiency of packet processing in resource-constrained nodes (e.g. software routers) can be strongly increased through parallel processing with commodity hardware based on multi-core processors. However, intra-node resource contention can have a strong negative impact on the corresponding network node. We describe how multi-core software routers can be optimized for low latency support by utilizing the technologies available in commodity PC hardware. For the analysis we used our approach for modeling of resource contention in resource-constrained nodes which is also implemented as the resource-management extension module for ns-3. Based on that, we derived a specific software router model which we used to optimize the performance. Our measurements show that the configuration of a software router has significant influence on the performance. The results can be used for parameter tuning in such systems.
Cited by 5
Xiangyu Gao, Raghunathan, Divya, Ruijie Fang et al. · Zenodo (CERN European Organization for Nuclear Research) · 2023
CaT compiler source code
Cited by 0Open access
Paul Chaignon · theses.fr (ABES) · 2019
Multi-tenant networks enable applications from multiple, isolated tenants to communicate over a shared set of underlying hardware resources. The isolation provided by these networks is enforced at the edge: end hosts demultiplex packets to the appropriate virtual machine, copy data across memory isolation boundaries, and encapsulate packets in tunnels to isolate traffic over the datacenter's physical network. Over the last few years, the growing demand for high performance network interfaces has pressured cloud providers to build more efficient multi-tenant networks. While many turn to specialized, hard-to-upgrade hardware devices to achieve high performance, in this thesis, we argue that significant performance improvements are attainable in end-host multi-tenant networks, using commodity hardware. We advocate for a consolidation of network functions on the host and an offload of specific tenant network functions to the host. To that end, we design Oko, an extensible software switch that eases the consolidation of network functions. Oko includes an extended flow caching algorithm to support its runtime extension with limited overhead. Extensions are isolated from the software switch to prevent failures on the path of packets. By avoiding costly redirections to separate processes and virtual machines, Oko halves the running cost of network functions on average. We then design a framework to enable tenants to offload network functions to the host. Executing tenant network functions on the host promises large performance improvements, but raises evident isolation concerns. We extend the technique used in Oko to provide memory isolation and devise a mechanism to fairly share the CPU among offloaded network functions with limited interruptions.
Cited by 0Open access
David Whyte, Evangelos Kranakis, P. C. Van Oorschot · 2010
Pick a random IP address � Most connections today: Name servers � No DNS request = worm! Detecting DNS Requests
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Waldo Nogueira, Andreas Giese, Bernd Edler et al. · 2006
Current speech processing strategies for cochlear implants use a filterbank which decomposes the audio signals into multiple frequency bands each associated with one electrode. Pitch perception with cochlear implants is related to the number of electrodes inserted in the cochlea and to the rate of stimulation of these electrodes. The filterbank should, therefore, be able to analyze the time-frequency features of the audio signals while also exploiting the time-frequency features of the implant. This study investigates the influence on speech intelligibility in cochlear implant users when filterbanks with different time-frequency resolutions are used. Three filterbanks, based on the structure of a wavelet packet transform but using different basis functions, were designed. The filterbanks were incorporated into a commercial speech processing strategy and were tested on device users in an acute study. 1.
Cited by 0
Hasanin Harkous, Michael Jarschel, Mu He et al. · IEEE Transactions on Network and Service Management · 2020
Data plane programmability brings network flexibility to a new level. However, it introduces the complexity of the data path's program as a new factor that influences packet forwarding latency and thus devices' performance. Accurate identification of the relation between data path complexity and packet forwarding latency enables the design and management of networks with predictable performance. In this article, we leverage the characteristics of P4 programming language to provide a method for estimating the packet forwarding latency as a function of the data path program. We analyze the impact of different P4 constructs on packet processing latency for three state-of-the-art P4 devices: Netronome SmartNIC, NetFPGA-SUME, and T4P4S DPDK-based software switch. Besides comparing the performance of these three targets, we use the derived results to propose a method for estimating the average packet latency, at compilation time, of arbitrary P4-based network functions implemented using the surveyed P4 constructs. The proposed method is finally validated using a set of realistic network functions, which shows that our method estimates the average packet latency with sub-microsecond precision.
Cited by 48Open access
Alessandra Fais, Giuseppe Lettieri, Gregorio Procissi et al. · Sensors · 2021
One of the most challenging tasks for network operators is implementing accurate per-packet monitoring, looking for signs of performance degradation, security threats, and so on. Upon critical event detection, corrective actions must be taken to keep the network running smoothly. Implementing this mechanism requires the analysis of packet streams in a real-time (or close to) fashion. In a softwarized network context, Stream Processing Systems (SPSs) can be adopted for this purpose. Recent solutions based on traditional SPSs, such as Storm and Flink, can support the definition of general complex queries, but they show poor performance at scale. To handle input data rates in the order of gigabits per seconds, programmable switch platforms are typically used, although they offer limited expressiveness. With the proposed approach, we intend to offer high performance and expressive power in a unified framework by solely relying on SPSs for multicores. Captured packets are translated into a proper tuple format, and network monitoring queries are applied to tuple streams. Packet analysis tasks are expressed as streaming pipelines, running on general-purpose programmable network devices, and a second stage of elaboration can process aggregated statistics from different devices. Experiments carried out with an example monitoring application show that the system is able to handle realistic traffic at a 10 Gb/s speed. The same application scales almost up to 20 Gb/s speed thanks to the simple optimizations of the underlying framework. Hence, the approach proves to be viable and calls for the investigation of more extensive optimizations to support more complex elaborations and higher data rates.
Cited by 3Open access
Paolo Giaccone · 2015
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Jiarong Xing, Yiming Qiu, Kuo-Feng Hsu et al. · 2023
SmartNICs are on the rise as a packet processing platform, with the trend towards a uniform P4 programming model. However, unleashing SmartNIC packet processing performance in P4 is a formidable task. Traditional SmartNIC optimizations rely on low-level program tuning, but P4 abstractions operate at one level above. At the same time, today's P4 optimizations primarily focus on resource packing rather than performance tuning. We develop Pipeleon, an automated performance optimization framework for P4 programmable SmartNICs. We introduce techniques that are tailored to the performance characteristics of SmartNICs, and further leverage dynamic workload patterns for profile-guided optimization. Pipeleon pinpoints program hotspots at the P4 level and computes runtime optimization plans to specialize the program layout based on the latest profile. We have prototyped Pipeleon and applied it to optimize two popular P4 SmartNICs---Nvidia BlueField2 and Netronome Agilio CX---as well as a software SmartNIC emulator extended based on BMv2. Our results show that Pipeleon significantly improves SmartNIC packet processing performance in realistic scenarios.
Cited by 21
Wai, PKA, Xu, L, Chan, LYS et al. · PolyU Institutional Research Archive (Hong Kong Polytechnic University) · 2010
Inventor name used in this publication: Lai Yin Chan
Cited by 0Open access
Cristian Soviani · 2007
Packet processing is an essential function of state-of-the-art network routers and switches. Implementing packet processors in pipelined architectures is a well-known, established technique, albeit different approaches have been proposed. The design of packet processing pipelines is a delicate trade-off between the desire for abstract specifications, short development time, and design maintainability on one hand and very aggressive performance requirements on the other. This thesis proposes a coherent design flow for packet processing pipelines. Like the design process itself, I start by introducing a novel domain-specific language that provides a high-level specification of the pipeline. Next, I address synthesizing this model and calculating its worst-case throughput. Finally, I address some specific circuit optimization issues. I claim, based on experimental results, that my proposed technique can dramat-ically improve the design process of these pipelines, while the resulting performance matches the expectations of hand-crafted design. The considered pipelines exhibit a pseudo-linear topology, which can be too re-strictive in the general case. However, especially due to its high performance, such an architecture may be suitable for applications outside packet processing, in which case some of my proposed techniques could be easily adapted. Since I ran my experiments on FPGAs, this work has an inherent bias towards that technology; however, most results are technology-independent.
Cited by 0
Jiaxin Lei, Manish Munikar, Kun Suo et al. · 2021
Container networking, which provides connectivity among containers on multiple hosts, is crucial to building and scaling container-based microservices. While overlay networks are widely adopted in production systems, they cause significant performance degradation in both throughput and latency compared to physical networks. This paper seeks to understand the bottlenecks of in-kernel networking when running container overlay networks. Through profiling and code analysis, we find that a prolonged data path, due to packet transformation in overlay networks, is the culprit of performance loss. Furthermore, existing scaling techniques in the Linux network stack are ineffective for parallelizing the prolonged data path of a single network flow.
Cited by 20Open access
Christian Hermsmeyer, Haoyu Song, R. Schlenk et al. · Bell Labs Technical Journal · 2009
Driven by media-rich and bandwidth-intensive Internet applications, 100 Gigabit Ethernet embodies the next logical and necessary line speed following 10G/40G, although enormous challenges exist. Can today's device technologies scale, or will new, disruptive approaches be required to overcome throughput and power density limitations? The evolution of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technology was analyzed concerning speed, density, power, and pin interfacing. While clock frequencies cannot keep up with the higher interface speeds, massive parallelism and deep pipelining are needed to scale the throughput. The state-of-the-art architectures and algorithms for every aspect of packet processing are described. In addition, we look at alternative memory concepts and cover some emerging technologies: asynchronous FPGAs as a means for boosting the system clock and serial interfaces reducing the pin count between devices. Thereby, economic considerations limit the choice between the options. We conclude that although significant effort is necessary in terms of device and board technology, economic 100G networking is viable.
Cited by 22
Patrick Eugster, Kirill Kogan, Sergey Nikolenko et al. · Journal of Parallel and Distributed Computing · 2016
Cited by 3
Yan Sun · Research Exchange (Washington State University) · 2011
Rapid expansion of the Internet has led to the exponential growth of requirement for highspeed packet processing, including both header processing and payload processing.In network applications such as Routers, Firewalls and Intrusion Detection Systems (IDS), there are three important issues needed to be designed efficiently to support today's high speed network: IP route lookup, packet classification and deep packet inspection.And these three procedures are usually implemented as different components, which make packet processing too slow to meet high-speed network's requirements.So how to design efficient packet processing components is very important.Special hardware, such as TCAMs, are widely used networking applications to achieve high throughput, but their disadvantages such as high cost and high power consumption usually limit their application.We focus on these issues and design efficient schemes to solve problems in today's and tomorrow's networks.Our approaches are based on the observation that all of these components contain redundancy and we can reduce the hardware consumption and increase the throughput if we can remove the redundancy efficiently.Furthermore, we remove the redundancy between different components to further improve the performance and we propose a new integrated architecture which integrates these three components efficiently.In order to design an efficient combined security gateway system, we first focus on how to design efficient three individual components, including routing table lookup, packet classification
Cited by 0Open access
Abbas Ramazani, F. Monteiro, Camille Diou et al. · 2005
The design of high performance application-specific processors is the bottleneck in many applications. In critical high data rate network devices such as modems and other end-user interfaces, the packet forwarding engine requires both high degree of flexibility (to support large number of protocols) as well as extremely high performance (to be able to support Gigabit processing). While hardware application-specific designs can cope with performance, they lack flexibility. Although software based solutions could be ideal to meet flexibility and low cost constraints, unfortunately, they miss the speed performance requirement. The main goal of this paper is to present an architectural model to design a new processor architecture based on multiple cores and specific dedicated hardware units. In particular, we propose a new model which takes into account network protocols characteristics and input traffic nature to meet performance and cost requirements.
Cited by 1
2008
on the Pentium ® M microprocessor A majority of the current and next generation server applications (web services, e-commerce, storage, etc.) employ TCP/IP as the communication protocol of choice. As a result, the performance of these applications is heavily dependent on the efficient TCP/IP packet processing within the termination nodes. This dependency becomes even greater as the bandwidth needs of these applications grow from 100 Mbps to 1Gbps to 10Gbps in the near future. Motivated by this, our work presented in this paper focuses on the following: (a) to understand the performance behavior of the various modes of TCP/IP processing, (b) to analyze the underlying architectural characteristics of TCP/IP packet processing and (c) to quantify the computational requirements of the TCP/IP packet processing component within realistic workloads. We achieve these goals by performing an in-depth analysis of packet processing performance on Intel’s state-of-the-art low power Pentium ® M microprocessor running the Microsoft Windows * Server 2003 operating system. Some of our key observations are – (i) that the mode of TCP/IP operation can significantly affect the performance requirements, (ii) that transmit-side processing is largely computeintensive as compared to receive-side processing which is more memory-bound and (iii) that the computational requirements for sending/receiving packets can form a substantial component (28 % to 40%) of commercial server workloads. From our analysis, we also discuss architectural as well as stack-related improvements that can help achieve higher server network throughput and result in improved application performance. I.
Cited by 0
Dong Lin, Advisor Prof, Boon Thau Loo et al. · 2011
Research Interest My research centers around distributed system, parallel computing architecture, and software-defined networks.
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