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About 10,000 papers for “Parallel array”

Parallel factor analysis in sensor array processing

Nicholas D. Sidiropoulos, Rasmus Bro, Georgios B. Giannakis · IEEE Transactions on Signal Processing · 2000

This paper links multiple invariance sensor array processing (MI-SAP) to parallel factor (PARAFAC) analysis, which is a tool rooted in psychometrics and chemometrics. PARAFAC is a common name for low-rank decomposition of three- and higher way arrays. This link facilitates the derivation of powerful identifiability results for MI-SAP, shows that the uniqueness of single- and multiple-invariance ESPRIT stems from uniqueness of low-rank decomposition of three-way arrays, and allows tapping on the available expertise for fitting the PARAFAC model. The results are applicable to both data-domain and subspace MI-SAP formulations. The paper also includes a constructive uniqueness proof for a special PARAFAC model.

Cited by 617

Channel reduction in massive array parallel MRI

Shuo Feng, Jim Ji · 2009

This paper presents a method to explore the flexibility of channel reduction in k-domain parallel imaging with massive arrays to improve the computation efficiency. MCMLI and GRAPPA are k-domain reconstruction methods that use a neighborhood of PE columns, FE line(s) and all channels in the interpolation kernels. For massive array which contains a large number of element coils computation cost can be a significant problem. In this paper, channel selection and reduction is performed according to the correlation between channel images for individual channel reconstructions. Simulation results show that the proposed channel reduction algorithm can achieve similar or improved reconstruction quality with significantly reduced computation for massive arrays with localized sensitivity.

Cited by 6

Data Parallel Performance Optimizations Using Array Aliasing

Charlie Hu, S. Lennart Johnsson · 1997

. The array aliasing mechanism provided in the Connection Machine Fortran (CMF) language and run--time system provides a unique way of identifying the memory address spaces local to processors within the global address space of distributed memory architectures, while staying in the data parallel programming paradigm. We show how the array aliasing feature can be used effectively in optimizing communication and computation performance. The constructs we present occur frequently in many scientific and engineering applications, and include various forms of aggregation and array reshaping through array aliasing. The effectiveness of the optimization techniques is demonstratedon an implementationof Anderson's hierarchicalO(N) N --body method. We also suggest a way of implementing the array aliasing feature in HPF by extending the semantics of the RESHAPE intrinsic function of Fortran 90 to include possible aliasing relationship between the parameter and returning arrays. Key words. Data pa...

Cited by 0

Figure 9: Parallel Disk Array Simulation Enforcing

2008

Arrival requests for video with resolution QoS modeled with poisson statistics. Disk model based on disk drive specifications to simulate disk latencies. Scalable MPEG2 trace data accessed by disks. Measurement to verify interactivity delay QoS

Cited by 0

Microstrip Loop Array (MLA) for Parallel Imaging

Shen, GG, Wei, J, Qu, P et al. · The HKU Scholars Hub (University of Hong Kong) · 2010

The microstrip loop array (MLA), an improved version of planar strip array, is proposed which take advantage of loop geometry. Without much loss of the
\nwell-decoupling benefit of strip line arrays, the proposed microstrip loop arrays have well-localized sensitivity profiles which are more suitable for parallel
\nimaging. Simulation and experiment results show that microstrip loop coils have sensitivity profiles like conventional loop coils, while the mutual coupling
\nis 10-20dB less at same distances. A sensitivity-encoded cardiac imaging was performed to demonstrate the suitability of MLA for parallel imaging.

Cited by 0Open access

A massively parallel diagonal-fold array processor

G.G. Pechanek, J.G. Delgado-Frias, S. Vassiliadis · 2002

Image processing for multimedia workstations is a computationally intensive task typically requiring special purpose hardware, for example a nearest neighbor mesh parallel machine organization. One type of nearest neighbor mesh computer consists of a K /spl times/ K square array of Processor Elements (PEs) where each PE is connected to the North, South, East, and West PEs only. In a torus configuration, there are a total of 2K/sup 2/ PE interfaces. Under the assumption of SIMD operation with unidirectional message and data transfers between the PEs, it is possible to reconfigure the array by placing the symmetric PEs together and share the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. K/sup 2/ PE interfaces without affecting performance. This new machine organization is termed the Diagonal-Fold Mesh Array Processor, providing equivalent performance to a nearest neighbor mesh with half the wiring complexity for unidirectional data transferring algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 5

Perfect Latin Squares And Parallel Array Access

Kichul Kim, V.K.P. Kumar · 2005

A new nonlinear skewing scheme is proposed for parallel array access. We introduce a new Latin square(perfect Latin square) which has several properties useful for parallel array access. A sufficient condition for the existence of perfect Latin squares and a simple construction method for perfect Latin squares are presented. The resulting skewing scheme provides conflict free access to various subsets of an N x N array using N memory modules. When the number of memory modules is an even power of two, address generation is performed in constant time using a simple circuit. This scheme is the first memory scheme that achieves constant time access to rows, columns, diagonals, and N/ sup 1/2/ x N/sup 1/2/ subarrays of an N x N array using the minimum number of memory modules.

Cited by 8

Parallel scan as a multidimensional array problem

Artjoms Šinkarovs, Sven‐Bodo Scholz · 2022

For many algorithms, it is challenging to identify a suitable parallel version, as the design space is typically very large. In this paper we demonstrate how rank-polymorphic array languages can be used as a tool to explore such design spaces through concise high-level specifications. If input data can be organised into a multi-dimensional array, and the algorithm can be stated as a recursive traversal over sub-arrays, array languages offer a lot of expressive power. The reason for this is that array shapes can be used to guide recursive traversals. Conciseness of specifications comes from array reshapes that move the desired elements into canonical hyperplanes.

Cited by 7Open access

Optimum design of parallel dipole antenna array

Yihong Qi, Li Zhu · 2002

The inaccuracy of the array amplitude, phase and location is formulated as a tolerance problem, and the mutual coupling is computed by the moment method. An accurate optimum design method for parallel dipole array is presented. The factors affecting the realizable high performance of the antenna are discussed and mathematically formulated. For the parallel dipole array, the worst-case tolerance optimization method is used for the design and the mutual coupling effect is considered by means of a transformation.

Cited by 0

Watershed parallel algorithm for asynchronous processors array

B. Galilee, Franck Mamalet, Marc Renaudin et al. · 2003

A joint algorithm-architecture analysis leads to a new version of picture segmentation system adapted to multimedia mobile terminal constraints. The asynchronous processors network, with a granularity level of one processor per pixel, based on data flow model, takes less than 10 /spl mu/s to segment a SQCIF $88*72 pixels - image (about 2000 times faster than the classical sequential watershed algorithms). The main originality of the proposed algorithm is only one global synchronization point is needed in order to complete the segmentation transformation, instead of the three (or more) classical points: minima detection, labelization and flooding. Our system tends to cope with multimedia mobile phones constraints, i.e. real time computing circuit, low power. We have simulated and validated this system thanks to "SystemC" library; VHDL synchronous prototyping shows up results accordingly.

Cited by 8

Standardized parallel sorting on SIMD array processor

Tianzhen Wang, Li Zhou, Qin Xiozhen · 2002

We present the standardized parallel sorting algorithm. Instead of the most basic CCI (compare and conditional interchange) operation in traditional sorting algorithms, this algorithm compares sorting data with a standard value sequence simultaneously and synchronously on an SIMD array processor. The algorithm possesses three significant advantages. First, the running time T is independent of the problem size, T=0(1). The second attractive feature of the algorithm is that it is not necessary to build a communication network between PEs. Finally, no bottleneck occurs in output. We have implemented the algorithm in an SIMD array processor that is designed by our research group. The experiment verifies all the theoretical predictions. For these merits the algorithm is of significance in both theory and practice.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 0

Parallel Calibration for Sensor Array Radio Interferometers

Martin Brossard, Mohammed Nabil El Korso, Marius Pesavento et al. · arXiv (Cornell University) · 2016

In order to meet the theoretically achievable imaging performance, calibration of modern radio interferometers is a mandatory challenge, especially at low frequencies. In this perspective, we propose a novel parallel iterative multi-wavelength calibration algorithm. The proposed algorithm estimates the apparent directions of the calibration sources, the directional and undirectional complex gains of the array elements and their noise powers, with a reasonable computational complexity. Furthermore, the algorithm takes into account the specific variation of the aforementioned parameter values across wavelength. Realistic numerical simulations reveal that the proposed scheme outperforms the mono-wavelength calibration scheme and approaches the derived constrained Cramér-Rao bound even with the presence of non-calibration sources at unknown directions, in a computationally efficient manner.

Cited by 4Open access

Scattering from periodic array of parallel strips

Hao Liu · Spectrum Research Repository (Concordia University) · 2001

The field distribution between strips in a periodic array of parallel strips was modeled. The electric field integral equation (EFIE) together with method of moments was employed to solve the problem. The incident plane wave was assumed to be transverse magnetic (TM) and transverse electric (TE). The effect of the incident angle on the field between strips was investigated. For comparison, an array of the same configuration but containing a finite number of parallel strips was also modeled using the EFIE and solved via the method of moments. Good agreement between the results from the periodic array and the finite array was found even when the number of strips is small. It is also found that the presence of the ground plane does not have much effect on the field distribution, but only raises the field strength level when the observer is located below the top of the parallel strips. The results are of interest for cellular mobile radio community in predicting the range dependence of a signal from a base station antenna, when propagating in built up residential area.

Cited by 1Open access

Parallel vision algorithms using sparse array presentations

Ravi V. Shankar, Ravi V. Shankar, Ravi V. Shankar et al. · 1993

Abstract: Sparse arrays are arrays in which the number of non-zero elements is a small fraction of the total number of array elements. This paper presents computer vision algorithms using sparse representations for arrays. The parallel architecture considered is a hypercube. The algorithms can be easily modified for other architectures like the mesh. We assume that the architecture is SIMD, i.e., all PEs work under the control of a single control unit. 1

Cited by 0