Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 6,839 papers for “Processor array”

Wavefront array processor for video applications

Ulrich Schmidt, S. Mehrgardt · 2002

A single-chip MIMD wavefront array processor for video applications is presented. The processor topology is an array of individually programmable mesh-connected cells; processors may be cascaded indefinitely in one or two dimensions. 12-b word width, superscalar RISC cell architecture, and the 125-MHz clock rate are tailored toward the requirement of digital video signal processing. The processor executes statically scheduled data flow programs, propagating data through the array in a wavefront-like manner. The processor is implemented in 0.8- mu double-metal CMOS. It has 1.2 million transistors, a chip area of 150 mm/sup 2/, a pin count of 124, and a maximum power dissipation of 8 W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 6

A sliding memory plane array processor

Myung Hoon Sunwoo, J.K. Aggarwal · IEEE Transactions on Parallel and Distributed Systems · 1993

A mesh-connected single-input multiple-data (SIMD) architecture called a sliding memory plane (SliM) array processor is proposed. Differing from existing mesh-connected SIMD architectures, SliM has several salient features such as a sliding memory plane that provides inter-PE communication during computation. Two I/O planes provide an I/O overlapping capability. Thus, inter-PE communication and I/O overhead can be overlapped with computation. Inter-PE communication time is invisible in most image processing tasks because the computation time is larger than the communication time on SliM. The ability to overlap inter-PE communication with computation, regardless of window size and shape and without using a coprocessor or an on-chip DMA controller is unique to SliM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 24

The cellular logic array image processor

M. J. Duff · The Computer Journal · 1977

Image processing and pattern recognition are tasks which are proving surprisingly resistant to automation. The majority of pattern recognition problems have still to be formulated in a manner sufficiently precise to allow effective programs to be written, whilst conventional approaches would seem to lead to a requirement for almost infinite processing times and storage area. Conventional serial digital computers are not well matched to the processes involved in pattern recognition. A processor composed of an array of logic elements interconnected with nearest neighbours and processing in parallel is better matched and can operate at greater speed. In order to explore fully the problems which are likely to be encountered in the use of parallel processing cellular logic arrays, several have been constructed and operated, the most recent of which, CLIP 3, is described.

Cited by 18Open access

Photorefractive Phased-Array-Radar Processor Dynamics

Robert T. Weverka, Anthony W. Sarto, Kelvin Wagner · 1993

Large adaptive, two dimensional phased-array radar antennas can consist of thousands of antenna elements, have GHz bandwidths, and must be able to steer and adapt the antenna beam rapidly in a dynamic signal environment.

Cited by 0

A transputer array based SAR processor

Andrew Knight, Michael Inggs · 2002

This work describes a synthetic-aperture radar (SAR) data processor based on a pipeline of transputers. The system is comprised of standard off-the-shelf transputer cards, a custom built transputer card with 64 MB RAM, and software written in OC-CAM. The SAR processor was designed as a general purpose processor for spaceborne and airborne SAR imagery.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 1

Optical logic array processor using shadowgrams

Jun Tanida, Yoshiki Ichioka · Journal of the Optical Society of America · 1983

On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performing a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an incoherent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LED’s. Experimental results demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, we construct an optical logic array processor that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.

Cited by 221

Systolic array processor for MVDR beamforming

J.G. McWhirter, T.J. Shepherd · IEE Proceedings F Radar and Signal Processing · 1989

An efficient systolic array for computing the minimum variance distortionless response (MVDR) from an adaptive antenna array is described. It is fully pipelined and based on a numerically stable algorithm which requires O(p2 + Kp) arithmetic operations per sample time, where p is the number of antenna elements and K is the number of look direction constraints.

Cited by 67

Array Processor Performance Under Directional Uncertainty

William S. Hodgkiss, L. W. Nolte · IEEE Transactions on Aerospace and Electronic Systems · 1978

Detection performance of four candidate receiver structures for the signal known except for direction (SKED) array problem is investigated. Included are the Bayes optimal detector, two estimate and plug structures, and a fixed estimate structure. Estimators considered are the maximum likelihood (ML) and maximum a posteriori (MAP). Performance degradation from optimal for the estimate and plug structures considered is shown to be significantly more severe the larger the array size.

Cited by 2

Optical logic array processor using shadowgrams

J. Ichioka, J. Tanida, Y. Ichioka · 1983

On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performing a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an inco-herent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LED&amp;apos;s. Experimental re-sults demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, we construct an optical logic array processor that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.

Cited by 0

Address Generation in an Array Processor

Nwachukwu · IEEE Transactions on Computers · 1985

This correspondence describes the implementation of a versatile hardware address indexing unit (AIU) capable of generating a multiplicity of address sequences for both array processing and array manipulation. The AIU utilizes a counter/multiplexer principle and incorporates an address logic for implementing real-value FFT based on a standard complex form.

Cited by 6

A data flow processor array system

Naohisa Takahashi, Makoto Amamiya · 1983

This paper presents the architecture of a highly parallel processor array system which executes programs by means of a data driven control mechanism. The data driven control mechanism makes it easy to construct an MIMD (multiple instruction stream and multiple data stream) system, since it unifies inter-processor data transfer and intra-processor execution control. The design philosophy of the data flow processor array system presented in this paper is to achieve high performance by adapting a system structure to operational characteristics of application programs, and also to attain flexibility through executing instructions based on a data driven mechanism. The operational characteristics of the proposed system are analyzed using a probability model of the system behavior. Comparing the analytical results with the simulation results through an experimental hardware system, the results of the analysis clarify the principal effectiveness of the proposed system. This system can achieve high operation rates and is neither sensitive to inter-processor communication delay nor sensitive to system load imbalance.

Cited by 21

Ring Array Processor (RAP): Software Architecture

Jeff Bilmes, Phil Kohn · 1991

The design and implementation of software for the Ring Array Processor (RAP), a high performance parallel computer, involved development for three hardware platforms: Sun SPARC workstations, Heurikon MC68020 boards running the VxWorks real-time operating system, and Texas Instruments TMS320C30 DSPs. The RAP now runs in Sun workstations under UNIX and in a VME based system using VxWorks. A flexible set of tools has been provided both to the RAP user and programmer. Primary emphasis has been placed on improving the efficiency of layered artificial neural network algorithms. This was done by providing a library of assembly language routines, some of which use node-custom compilation. An object-oriented RAP interface in C++ is provided that allows programmers to incorporate the RAP as a computational server into their own UNIX applications. For those not wishing to program in C++, a command interpreter has been built that provides interactive and shell-script style RAP manipulation. 1 In...

Cited by 0