Lu Yin, Peng Yang, Tao Dong et al. · IEEE Antennas and Wireless Propagation Letters · 2024
In this letter, we introduce a low-cost, independently dual-polarized electronically scanned array. It incorporates two orthogonal microstrip dipoles with miniaturized cascaded 90<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> phase shifter to achieve a dual-channel configuration, which improves the capabilities of antenna. By manipulating the states of p-i-n diodes, it becomes possible to precisely control over the radiation patterns. A 2-D planar array consisting of 64 active elements operating at a working frequency from 4.8 GHz to 4.9 GHz is fabricated and measured. Shared 2-bit phase control allows for the simultaneous steering of dual-polarized beams in the same direction. This array provides a wide range of beam scanning within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm {\text{45}}^\circ$</tex-math></inline-formula> allowing for the implementation of scannable beams. The measured results agree well with the simulation ones, demonstrating the excellent scanning performance of the antenna array.
Cited by 1
Jianjun Huang, Hao Huang, Kang Li et al. · 2024
Direction of Arrival (DoA) estimation is a key technology in array signal processing. One-bit quantization is a popular method for reducing hardware costs in DoA estimation. However, one-bit quantization introduces significant quantization noise, which can greatly impact the accuracy of DoA estimation. Therefore, we propose a method for DoA estimation based on nested linear array (NLA) and mixed one-bit quantization. This method combines all one-bit quantization and full precision quantization, aiming to leverage the advantages of all one-bit quantization while preserving more signal information, thereby maintaining higher estimation accuracy. Additionally, by employing NLA, the system performance is enhanced and hardware costs are reduced, effectively overcoming the limitations of uniform linear array (ULA). We derived the principles of the covariance matrix for mixed one-bit quantization used in DoA estimation and the calculation method for its CRB. Simulation experiments demonstrate that compared to all one-bit quantization, this method significantly improves DoA estimation performance and achieves a lower Cramer-Rao Bound (CRB). The proposed method can achieve a good trade off between hardware costs and estimation accuracy.
Cited by 0
Robert A. Heaton, Donald W. Blevins, E M Davis · IEEE Journal of Solid-State Circuits · 1990
An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1- μm CMOS design contains over 1.1-million transistors on an 11.0-mm*11.7-mm die.
Cited by 12
Jaejin Lee, Gi-Yong Song · 2004
To achieve higher degree of concurrency in a systolic array, it is desirable to make cells of a systolic array themselves a systolic array as well, leading to a structure called super-systolic array. This paper proposes a bit-level super-systolic FIR filter with a FPGA-based bit-serial semi-systolic multiplier. Compared to the word-level systolic FIR filter and corresponding super-systolic filter, the proposed design is very compact in that it needs only two 1-bit I/O ports in addition to significant improvement on hardware complexity. The input to the implementation proposed in this paper is a sequence of bit-string in contrast to the distributed arithmetic which assumes input of parallel bit-string. Also, the arrangement of the cells of a semi-systolic multiplier is tuned to fit to the structure of the FPGA. (This work was done as a part of Information & Communication fundamental Technology Research Program supported by Ministry of Information & Communication in republic of Korea.
Cited by 1
Yeshudas Muttu, Lokesh Kumar Bramhane, Amol D. Rahulkar et al. · 2024
This paper presents the implementation and performance analysis of five digital parallel array multipliers: Conventional Array Multiplier, Modified Braun’s Multiplier, Vedic Multiplier, Booth’s Multiplier, and Baugh-Wooley Multiplier. It details the design principles, algorithms, and hardware implementations of each multiplier. The multipliers are evaluated based on speed, area, and power consumption via simulation using Xilinx Vivado software with Artix-7 FPGA Board. The results highlight the trade-offs in each design and provide insights into their suitability for various digital signal processing applications.
Cited by 2
Bo Yin, Shubin Wang, Yun Li et al. · Progress In Electromagnetics Research M · 2024
The application scenarios of near-field focusing metasurfaces usually require scanning the target area. Passive metasurface requires a turntable to complete scanning due to its limited functionality. The active metasurface typically has a high cost because it needs to load PIN diodes. To address this issue, the article introduces a 1-bit reconfigurable metasurface that can achieve multi-focus tunability under fixed polarization through a rotating array. The 1-bit polarization-independent metasurface unit consists of three layers of metal. The top layer of the unit consists of three rectangular patches in the X-direction the middle layer is a cross-shaped patch structure and the bottom layer is a metal ground. The cross-shaped structure in the middle layer can easily provide the 1-bit reflection phase required for two orthogonal polarizations independently. Using a vertically polarized horn to illuminate the metasurface, the top layer's X-direction rectangular patches do not provide phase for vertical polarization. By rotating the array where the cross-shaped patches are located by 90 , the phase shift provided can achieve two focal points. On this basis, rotate the upper array by 90 , making the rectangular patches change from the X-direction to the Y -direction. Meanwhile, the current of the cross-shaped patches is blocked under vertical polarization illumination. By changing the upper rectangular patches, a third independent phase can be provided. After size optimization, a third focus can be formed. The proposed 1-bit focusing-adjustable metasurface array has a simple structure, low cost, and enhanced utilization rate of the metasurface array. It has a high application prospect in projects such as microwave imaging.
Cited by 1Open access
Mohammad Nasim Imtiaz Khan, Swaroop Ghosh, Radha Krishna Aluru et al. · arXiv (Cornell University) · 2016
Crossbar arrays using emerging non-volatile memory technologies such as Resistive RAM (ReRAM) offer high density, fast access speed and low-power. However the bandwidth of the crossbar is limited to single-bit read/write per access to avoid selection of undesirable bits. We propose a technique to perform multi-bit read and write in a diode-STTRAM (Spin Transfer Torque RAM) crossbar array. Simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read and thus reduce the sneak path through the half-selected cells. In write operation, the half-selected cells are biased with a pulse voltage source which increases the write latency of these cells and enables to write 2-bits while keeping the half-selected bits undisturbed. Simulation results indicate biasing the half-selected cells by 700mV can enable reading as much as 512-bits while sustaining 512x512 crossbar with 2.04 years retention. The 2-bit writing requires pulsing by 50mV to optimize energy.
Cited by 3Open access
Chin-Liang Wang, H. S. Tsou · 2003
A bit-serial bit-level systolic array based on a new scheme for multiplication and inner product computation is presented to implement delayed least-mean-square (DLMS) adaptive N-tap finite-impulse-response (FIR) filters. The architecture has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of ((4B+N/2+4)/2B) in the filter coefficient adaptation, where (x) is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance with proper selection of the step size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0
Krikidis, Ioannis · arXiv (Cornell University) · 2015
This letter deals with the opportunistic beamforming (OBF) scheme for multi-antenna downlink with spatial randomness. In contrast to conventional OBF, the terminals return only 1-bit feedback, which is powered by wireless power transfer through a rectenna array. We study two fundamental topologies for the combination of the rectenna elements; the direct-current combiner and the radio-frequency combiner. The beam outage probability is derived in closed form for both combination schemes, by using high order statistics and stochastic geometry.
Cited by 0Open access
Jingjing Wang, Rongjin Xu, Chixiao Chen et al. · 2015
This paper presents a low power 9-bit 100MS/s successive approximation register analog-to-digital converter (SAR ADC) due to the custom capacitor array. In this capacitor array, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell. A beneficial improvement to capacitor array structure makes some difference too. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 100MS/s, the layout simulation of proposed SAR ADC achieves an ENOB of 8.54bit, an SNDR of 53.15dB, an SFDR of 63.14dB and power consumption of 0.43mW under Nyquist sampling. The FOM of the SAR ADC is low to 8.63fJ/conv.
Cited by 0
Antonio Clemente, Laurent Dussopt, Ronan Sauleau et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2011
International audience
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Yu Wang, Zhiyong Cheng, Quanjun Song · 2025
Cross-dipole array consists of two scalar arrays orthogonal to each other. With one-bit measurements, we can generate two covariance matrices and two cross-covariance matrices of the cross-dipole array signals. In the developed DOA estimation with one-bit measurements, only two covariance matrices are combined to perform direction-of-arrival (DOA) estimation. This paper further utilizes cross-covariance matrices for DOA estimation. To do this, we first study the reconstruction of two cross-covariance matrices from one-bit measurements. Based on the analyses of four covariance matrices, we then formulate virtual array datum consisting of four virtual snapshots by difference array technique, called parallel coarray signals. We employ the spatial-smoothing technique on the parallel coarray signals to perform the DOA estimation. Numerical results show that the proposed approach have superior performance to that using only two covariance matrices.
Cited by 0
Qiuyang Lu, Peng Gu, Z. H. Cao et al. · 2024
A 1-bit linearly polarized widedband high-efficiency reconfigurable transmit-array is proposed, consisting of magnetoelectric dipole and butterfly shaped metal patch. The 180° phase difference is achieved by controlling the state of the PIN diodes. A 12 × 12 array was designed and tested in HFSS, and the test results showed that two-dimensional beam scanning can be achieved with a scanning range of ±40°. The maximum gain in the broadside direction can reach 22.38dBi, the aperture efficiency is 34.7%, and the 3dB gain bandwidth is 26.2%.
Cited by 0
Zhibing Pi, G. Fan, Jingyuan Zhang et al. · 2025
This paper introduces a 6-bit digital step attenuator (DSA) designed with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.12 \mu \mathrm{m}$</tex> GaN-on-SiC HEMT technology. The design incorporates six distinct attenuation units optimized for low insertion loss, high attenuation accuracy, and minimal phase error. The simulation results indicate RMS amplitude and phase errors of 0.26 dB and 3.7°, respectively, and the architecture achieves an insertion loss of less than 3.72 dB within the frequency range of 5 to 14 GHz. The deisgned DSA is a compact, high-performance solution that is well-suited to phased-array applications.
Cited by 0
Hua Fan, Peng Lei, Quanyuan Feng et al. · Circuits Systems and Signal Processing · 2022
Cited by 2
Jonathan S. Ward, J.V. McCanny, J.G. McWhirter · IEE Proceedings F Communications Radar and Signal Processing · 1985
A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbour interconnections, regularity and high throughput. The short interconnections in this method contrast favourably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.
Cited by 5
Peter S. Guilfoyle, W. J. Wiley · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1986
This manuscript represents the second paper in a series of publications describing alternative combinatorial logic based optical computing architectures. Within the first paper titled "Combinatorial Logic Based Optical Computing," justification for combinatorial logic is initially debated through the coupled use of extensive optical interconnects with the natural "and-or-invert" capability of most every optical system.1 This is followed by a simple example of an optical "text" processor, a word and phrase comparitor which can be used for massive text look-up and search. This demonstrates the ability to design a wide range of digital optical architectures capable of performing numerous, if not myriad, sets of digital functions other than mathmatical. The original paper continues to describe a digital optical full adder enhanced by the full global broadcast capability of optics. Finally, a 2 x 2 bit systolic multiplier is described for matrix processing where the limitations of the DMAC algorithm are finally overcome.2-5 The output is thus a full 4 bit binary weighted result.
Cited by 6
Mohammad Nasim Imtiaz Khan, Swaroop Ghosh · 2020
Crossbar arrays using emerging Non-Volatile Memory (NVM) technologies offer high density, fast access speed and low-power. However, the bandwidth of the crossbar is limited to single-bit read/write per access to avoid the selection of undesirable bits. In this work, we propose a technique to perform multi-bit read and write in a diode-MTJ (Magnetic Tunnel Junction) crossbar array. The simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read which in turn, reduces the sneak path through the half-selected cells. Results indicate biasing the half-selected cells by 700mV can enable reading as much as 512bits while sustaining 512×512 crossbar with 2.04 years retention. During write operation, the half-selected cells are biased with a pulse voltage source in addition to V/2 scheme which increases the write latency of these cells and enables writing 2 bits while keeping the half-selected bits undisturbed. The 2bit writing requires pulsing by 50mV to optimize energy.
Cited by 1
Yang Xiong, Zeyang Li, Fangqing Wen · 2020
Direction-of-arrival (DOA) estimation is an interesting research topic with various applications. Existing algorithms provide superior estimation performance, at the cost of accurate quantified measurements. In this paper, we stress the problem of 2D DOA estimation for uniform rectangular array using one-bit measurements. The relationship between the covariance matrices of one-bit measurement and that of the accurately quantified measurement is analyzed in detail, from which we find the existing tensor algorithm can be directly applied. As a result, a one-bit parallel factor analysis (PARAFAC) estimator is proposed. Simulation results show the effectiveness of the proposed method.
Cited by 3
Yanchang Gao, Gang Ni, Kun Wang et al. · 2020 9th Asia-Pacific Conference on Antennas and Propagation (APCAP) · 2020
A novel single-sideband (SSB) time-modulated technique with 2-bit phase shifters is proposed. The time-modulated module is implemented by adding periodic phase modulation to 2-bit phase shifters, which is simpler without performance loss compared to existing SSB time-modulated method. During one modulation period, four phase states (0, π/2, π, 3π/2) of 2-bit phase shifters are switched in sequence. After the modulation, the SSB time modulation is realized and the main power is distributed to the first harmonic component. The feasibility of the proposed method is verified by experiments. The undesired harmonics are efficiently suppressed. Meanwhile, ±40 beam scanning range are realized through the proposed module.
Cited by 16