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Multi-Resource Fair Queueing for Packet Processing

Ali Ghodsi, Vyas Sekar, Matei Zaharia et al. · 2012

Cited by 49

Application Layer Packet Processing Using PISA Switches

İsmail Bütün, Yusuf Kursat Tuncel, Kasım Öztoprak · Sensors · 2021

This paper investigates and proposes a solution for Protocol Independent Switch Architecture (PISA) to process application layer data, enabling the inspection of application content. PISA is a novel approach in networking where the switch does not run any embedded binary code but rather an interpreted code written in a domain-specific language. The main motivation behind this approach is that telecommunication operators do not want to be locked in by a vendor for any type of networking equipment, develop their own networking code in a hardware environment that is not governed by a single equipment manufacturer. This approach also eases the modeling of equipment in a simulation environment as all of the components of a hardware switch run the same compatible code in a software modeled switch. The novel techniques in this paper exploit the main functions of a programmable switch and combine the streaming data processor to create the desired effect from a telecommunication operator perspective to lower the costs and govern the network in a comprehensive manner. The results indicate that the proposed solution using PISA switches enables application visibility in an outstanding performance. This ability helps the operators to remove a fundamental gap between flexibility and scalability by making the best use of limited compute resources in application identification and the response to them. The experimental study indicates that, without any optimization, the proposed solution increases the performance of application identification systems 5.5 to 47.0 times. This study promises that DPI, NGFW (Next-Generation Firewall), and such application layer systems which have quite high costs per unit traffic volume and could not scale to a Tbps level, can be combined with PISA to overcome the cost and scalability issues.

Cited by 8Open access

Creating portable and efficient packet processing applications

Olivier Morandi, Fulvio Risso, Pierluigi Rolando et al. · Design Automation for Embedded Systems · 2011

Cited by 7

Fast Packet Processing on High Performance Architectures

ANTICHI, GIANNI · Electronic Theses and Dissertations Repository (University of Pisa) · 2011

The rapid growth of Internet and the fast emergence of new network applications have brought great challenges and complex issues in deploying high-speed and QoS guaranteed IP network. For this reason packet classification and network intrusion detection have assumed a key role in modern communication networks in order to provide Qos and security. In this thesis we describe a number of the most advanced solutions to these tasks. We introduce NetFPGA and Network Processors as reference platforms both for the design and the implementation of the solutions and algorithms described in this thesis. The rise in links capacity reduces the time available to network devices for packet processing. For this reason, we show different solutions which, either by heuristic and randomization or by smart construction of state machine, allow IP lookup, packet classification and deep packet inspection to be fast in real devices based on high speed platforms such as NetFPGA or Network Processors.

Cited by 0Open access

Stack Protection Mechanisms In Packet Processing Systems

Wu, Peng · Scholarworks (University of Massachusetts Amherst) · 2023

As the functionality that current computer network can provide is becoming complicated, a traditional router with application-specific integrated circuit (ASIC) implementation can't satisfy the flexibility requirements. Instead, a programmable packet forward system based on a general-purpose processor could provide the flexibility. While this system provides flexibility, a new potential security issue arises. Usually, software is involved as the packet forward system is programmable. The software's potential vulnerability, especially as to the remote exploits, becomes an issue of network security. In this thesis work, we proposed a software stack overflow vulnerability on click modular router and show how a disastrous denial-of-service attack on click modular router could be triggered by a single packet. In our research work, click modular router runs on Linux operating system based on general-purpose hardware. We actually showed that even a software router run within a modern operating system's protection is vulnerable by elaborate attack. And we checked the possible stack protection mechanisms on modern OS based on general-purpose hardware and proposed a possible stack protection mechanism for embedded OS.

Cited by 0Open access

Hierarchical Multiresource Fair Queueing for Packet Processing

Chaoqun You, Yangming Zhao, Gang Feng et al. · IEEE Transactions on Network and Service Management · 2022

Various middleboxes are ubiquitously deployed in networks to perform packet processing functions, such as firewalling, proxy, scheduling, etc., for the flows passing through them. With the explosion of network traffic and the demand for multiple types of network resources, it has never been more challenging on a middlebox to provide Quality-of-Service (QoS) guarantees to grouped flows. Unfortunately, all currently existing fair queueing algorithms fail in supporting hierarchical scheduling, which is necessary to provide QoS guarantee to the grouped flows of multiple service classes. In this paper, we present two new multi-resource fair queueing algorithms to support hierarchical scheduling, collapsed Hierarchical Dominant Resource Fair Queueing (collapsed H-DRFQ) and dove-tailing H-DRFQ. Particularly, collapsed H-DRFQ transforms the hierarchy of grouped flows into a flat structure for flat scheduling while dove-tailing H-DRFQ iteratively performs flat scheduling to sibling nodes on the original hierarchy. Through rigorous theoretical analysis, we find that both algorithms can provide hierarchical share guarantees to individual flows, while the upper bound of packet delay in dove-tailing H-DRFQ is smaller than that of collapsed H-DRFQ. We implement the proposed algorithms on Click modular router and the experimental results verify our analytical results.

Cited by 12Open access

OpenFlow transparent custom action extension by using Packet-In and click packet processing

Shogo Ando, Akihiro Nakao · 2016

Software-Defined Networking (SDN) is an emerging technology that controls network by using software. OpenFlow switches have predefined actions to be executed by the controller, but if any undefined actions need to be executed on given packets, they are transferred to the controller by the exception mechanism called Packet-In and processed there. When we execute undefined custom actions with Packet-In on the controller, there are three problems. (1) concentration of Packet-In messages, (2) latency of Packet-In message transfer and (3) incompatibility among controller frameworks. In this paper, we propose OpenFlow Click Action Extension (OFCAE), which provides sharing custom actions among various controller frameworks with low latency while keeping the compatibility with the OpenFlow architecture. We introduce Packet-In Proxy, which implements local Packet-In processing within the switch to alleviate the concentration of Packet-In messages. Furthermore, we propose Packet-In Of-floader to perform custom packet processing for Packet-In Proxy. We implement and evaluate the prototype of our proposed system and show a case of custom actions.

Cited by 3

Application-Driven Development of Concurrent Packet Processing Platforms

Christian Sauer, Matthias Gries, Jörg-Christian Niemann et al. · 2006

We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we have to trade off flexibility against costs and performance. Our methodology therefore focuses on characterizing the application domain as early as possible. With this input, we can narrow the design space to one major design trajectory that starts with the most flexible solution and refines the platform architecture systematically to meet performance and costs constraints. Our flow includes an efficient path to implementation in hardware and software. The software implementation framework takes a modular application description and generates code for embedded processors that can easily be ported to different platforms and used for profiling. Different communication architectures, co-processors, and specializations of programmable processing elements can be derived from profiling results to affect the platform hardware. A DSL access multiplexer (DSLAM) is used as an example throughout the paper to depict the different phases of our design process

Cited by 1

Speculative Protocol-Processing for High-Speed Packet Forwarding

Jürgen Foag · mediaTUM – the media and publications repository of the Technical University Munich (Technical University Munich) · 2004

Current network processors are VLSI-devices dedicated to high-speed packet forwarding. While their architectures are optimized for high throughput rates, they normally disregard protocol-processing delays which result from data dependencies inherent to encapsulated protocol-layers. The key to overcome this limitation is to speculatively dissolve these dependencies and to allow an accelerated control-path processing. This thesis comprises the entire framework of a speculative network processor conception, implementation and evaluation. Besides an generic evaluation, the benefit of the system is shown by system simulation. Utilizing the approach, a latency reduction of up to 14.9 percent can be achieved compared to traditional implementations.

Cited by 0Open access

Building Evolvable Networks : Flexible and Predictable Packet Processing

Mihai Dobrescu · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2015

Software packet-processing platforms- - network devices running on general-purpose servers-- are emerging as a compelling alternative to the traditional high-end switches and routers running on specialized hardware. Their promise is to enable the fast deployment of new, sophisticated kinds of packet processing without the need to buy and deploy expensive new equipment. This would allow us to transform the current Internet into a programmable network, a network that can evolve over time and provide a better service for the users. In order to become a credible alternative to the hardware platforms, software packet processing needs to offer not just flexibility, but also a competitive level of performance and, equally important, predictability. Recent works have demonstrated high performance for software platforms, but this was shown only for simple, conventional workloads like packet forwarding and IP routing. And this was achieved for systems where all the processing cores handle the same type/amount of traffic and run identical code, a critical simplifying assumption. One challenge is to achieve high and predictable performance in the context of software platforms running a diverse set of applications and serving multiple clients with different needs. Another challenge is to offer such flexibility without the risk of disrupting the network by introducing bugs, unpredictable performance, or security vulnerabilities. In this thesis we focus on how to design software packet-processing systems so as to achieve both high performance and predictability, while maintaining the ease of programmability. First, we identify the main factors that affect packet-processing performance on a modern multicore server-- cache misses, cache contention, load-balancing across processing cores-- and show how to parallelize the functionality across the available cores in order to maximize the throughput. Second, we analyze the way contention for shared resources-- caches, memory controllers, buses-- affects performance in a system that runs a diverse set of packet-processing applications. The key observation is that contention for the last-level cache represents the dominant contention factor and the performance drop suffered by a given application is mostly determined by the number of cache references/second performed by the competing applications. We leverage this observation and we show that such a system is able to provide predictable performance in the face of resource contention. Third, we present the result of working iteratively on two tasks: designing a domain-specific verification tool for packet-processing software, while trying to identify a minimal set of restrictions that packet-processing software must satisfy in order to be verification-friendly. The main insight is that packet-processing software is a good fit for verification because it typically consists of distinct pieces of code that share limited mutable state and we can leverage this domain specificity to sidestep fundamental scalability challenges in software verification. We demonstrate that it is feasible to automatically prove useful properties of software dataplanes to ensure a smooth network operation. Based on our results, we conclude that we can design software network equipment that combines both flexibility and predictability.

Cited by 0Open access

All-optical signal processing for optical packet switching

Geldenhuys, R, Liu, Y Yong, Calabretta, N Nicola et al. · TU/e Research Portal (Eindhoven University of Technology) · 2004

We present three optical signal processing functional blocks that enable 1×N optical packet switching. An ultrafast asynchronous multioutput all-optical header processor is demonstrated with a terahertz optical asymmetric demultiplexer in combination with a header preprocessor. It is shown that self-induced polarization rotation can be used for both the header processor and the header preprocessor. The second functional block is optical buffering. This is shown with both a laser neural network and a recirculating buffer. Related to this is a three-state all-optical memory based on coupled lasers, which increases the number of possible output states of an optical packet switch.\n© 2004 Optical Society of America

Cited by 0

hXDP: Efficient Software Packet Processing on FPGA NICs

Brunella, MS, Belocchi, G, Bonola, M et al. · IRIS Research product catalog (Sapienza University of Rome) · 2020

FPGA accelerators on the NIC enable the offloading of expensive packet processing tasks from the CPU. However, FPGAs have limited resources that may need to be shared among diverse applications, and programming them is difficult.We present a solution to run Linux's eXpress Data Path programs written in eBPF on FPGAs, using only a fraction of the available hardware resources while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized or completely removed, when targeting a purpose-built FPGA executor, thereby significantly improving performance. We leverage that to design hXDP, which includes (i) an optimizing-compiler that parallelizes and translates eBPF bytecode to an extended eBPF Instruction-set Architecture defined by us; a (ii) soft-CPU to execute such instructions on FPGA; and (iii) an FPGA-based infrastructure to provide XDP's maps and helper functions as defined within the Linux kernel.We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation is clocked at 156.25MHz, uses about 15% of the FPGA resources, and can run dynamically loaded programs. Despite these modest requirements, it achieves the packet processing throughput of a high-end CPU core and provides a 10x lower packet forwarding latency.

Cited by 0

DrawerPipe: A Reconfigurable Packet Processing Pipeline for FPGA

Junnan Li, Xiangrui Yang, Zhigang Sun · 2018

Cited by 1

Writing P4 compiler backend for packet processing engines

Balachandher Sambasivam, Maheswari Subramanian, Deb Chatterjee et al. · 2021

The advent of P4 as a protocol-independent and platform-independent network packet processing language has revolutionized the way networks are designed and the way networking devices are programmed. There are few programmable devices, whether ASICs or FPGA-based devices, that are designed with P4 programmability as the end goal right from the beginning. As a consequence, although these packet processing engines are programmable, writing a P4 compiler for these targets requires overcoming some technical challenges. Our team has worked on a variety of packet processing pipelines in recent years, in this article, we are presenting some of these challenges as well as the solutions we found to work around them.

Cited by 3

Optical packet switching and associated optical signal processing

Daniel J. Blumenthal, John E. Bowers, Yi‐Jen Chiu et al. · 2003

In this talk we will review functions for optical packet switching and ultra-fast network functions that can be handled using all-optical signal processing technologies. We will review research results utilizing ultra-fast all-optical nonlinear fiber wavelength converters and InP integrated optical wavelength converters. Application to all-optical label swapping and WDM/OTDM networks will be discussed.

Cited by 2

Isolation mechanisms for high-speed packet-processing pipelines

Tao Wang, Xiangrui Yang, Gianni Antichi et al. · arXiv (Cornell University) · 2021

Data-plane programmability is now mainstream. As we find more use cases, deployments need to be able to run multiple packet-processing modules in a single device. These are likely to be developed by independent teams, either within the same organization or from multiple organizations. Therefore, we need isolation mechanisms to ensure that modules on the same device do not interfere with each other. This paper presents Menshen, an extension of the Reconfigurable Match Tables (RMT) pipeline that enforces isolation between different packet-processing modules. Menshen is comprised of a set of lightweight hardware primitives and an extension to the open source P4-16 reference compiler that act in conjunction to meet this goal. We have prototyped Menshen on two FPGA platforms (NetFPGA and Corundum). We show that our design provides isolation, and allows new modules to be loaded without impacting the ones already running. Finally, we demonstrate that feasibility of implementing Menshen on ASICs by using the FreePDK45nm technology library and the Synopsys DC synthesis software, showing that our design meets timing at a 1GHz clock frequency and needs approximately 6% additional chip area. We have open sourced the code for Menshen's hardware and software at https://isolation.quest/.

Cited by 12Open access

Application of wavelet packet in gravity anomaly processing

Zhang Hong, Yangang Wu · 2012

Based on the advantages of the wavelet to separate regional field and local anomalies in MATLAB en- vironment , a high-precision regional-residual separation was finally realized. Analytical continuation and trend surface analysis are conventional methods for gravity anomaly separation. But the wavelet packet analysis in ana- lyzing gravity data can make the gravity anomaly to be computed at a higher precision. In this paper , wavelet packet method is used to process gravity anomaly data obtained in Laos , and the separation result is good. Dau- bechies wavelet series has a higher precision in the wavelet packet.

Cited by 1

Hybrid cache architecture for high-speed packet processing

Zhi Liu, Kai Zheng, Bin Liu · IET Computers & Digital Techniques · 2007

The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to effectively utilise them because of the explicit data movement between different memory levels. Also, the effectiveness of traditional cache in NPs needs to be improved. A memory hierarchy component, called split control cache, is presented that employs two independent low-latency memory stores to temporarily hold the flow-based and application-relevant information, exploiting the different locality behaviours exhibited by these two types of data. Just like conventional cache, data movement is manipulated by specially designed hardware so as to relieve the programmers from the details of memory management. Software simulation shows that compared with conventional cache, a performance improvement of up to 90% can be achieved by this scheme for OC-3c and OC-12c links.

Cited by 3

Offloading Packet Processing in a Combined Router/Server

Voravit Tanyingyong, Markus Hidell, Peter Sjödin · 2011

Despite the performance limitation with minimum-sized packet processing, a modern PC-based router can provide as competitive service as a specialized hardware router while offering more flexibility and possibility to extend beyond routing. We focus on a use case in which the PC-based router also functions as a server. In this paper, we propose an architecture to boost overall performance of the PC-based router by offloading packet processing tasks to the NIC. We introduce a fast path for packet forwarding based on caching of flow entries in on-board classification hardware on the NIC. We describe our design and present an experimental evaluation.

Cited by 3

Overlay Architectures for FPGA-Based Software Packet Processing

Martin Labrecque, Martin Labrecque · 2011

Packet processing is the enabling technology of networked information systems such as the Internet and is usually performed with fixed-function custom-made ASIC chips. As communication protocols evolve rapidly, there is increasing interest in adapting features of the processing over time and, since software is the preferred way of expressing complex computation, we are interested in finding a platform to execute packet processing software with the best possible throughput. Because FPGAs are widely used in network equipment and they can implement processors, we are motivated to investigate executing software directly on the FPGAs. Off-the-shelf soft processors on FPGA fabric are currently geared towards performing embedded sequential tasks and, in contrast, network processing is most often inherently parallel between packet flows, if not between each individual packet. Our goal is to allow multiple threads of execution in an FPGA to reach a higher aggregate throughput than commercially available shared-memory soft multi-processors via improvements to the underlying soft processor architecture. We study a number of processor pipeline organizations to identify which ones can scale to a larger number of execution threads and find that tuning multithreaded pipelines can provide compact cores with high throughput. We then perform a design space exploration of multicore soft systems, compare single-threaded and multithreaded designs to identify scalability limits and

Cited by 0