Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria · Electronics Letters · 2013
Proposed is a parallel array histogram architecture (PAHA) suitable for embedded implementations. The PAHA uses a register array instead of a memory block to store the histogram bins. In each step, M inputs can be processed in parallel to update the histogram bins without any additional latency. Also described is a second version of the PAHA with a flexible number of inputs, potentially avoiding the need for multiple PAHAs in a single application. Implementation results show that the architecture can achieve a super‐linear speed‐up of 43.75× for a 16‐way PAHA when compared to a software implementation in a general‐purpose processor.
Cited by 7Open access
Krishna Kunchithapadam, Barton P. Miller · Lecture notes in computer science · 1995
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Igor Milosavljević, M.A. Jabri · 2003
We present the ParAL system which compiles Matlab scripts into C programs with calls to a parallel run-time library. The novel feature of the compiler is the optimisation of array alignment which reduces or eliminates unnecessary communication overheads. We have evaluated this technique on several Matlab codes. For comparison, the same applications were hand-coded using the PBLAS library. The aligned codes were on average 43% faster then the misaligned codes, with the speedup factor of almost 4 achieved in some cases. This optimisation technique enabled ordinary Matlab scripts to run at a similar speed as manually optimised PBLAS codes.
Cited by 14
S. James Immanuel, D. G. Thomas, T. Robinson et al. · Lecture notes in computer science · 2017
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In Haskell, Sean Lee, Manuel M. T. Chakravarty et al. · 2012
We present a novel high-level parallel programming model for graphics processing units (GPUs). We embed GPU kernels as data-parallel array computations in the purely functional language Haskell. GPU and CPU computations can be freely interleaved with the type system tracking the two different modes of computation. The embedded language of array computations is sufficiently limited that our system can automatically isolate and extract these computations and compile them to efficient GPU code. In this paper, we outline our approach and present the results of a few preliminary benchmarks. 1.
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Frank Tsui · SMARTech Repository (Georgia Institute of Technology) · 1974
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Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov et al. · 2006
In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost. The applicability of our approach is tested in a case study with different interconnect topologies on an FPGA platform. The results show substantial flexibility gains with only marginal additional hardware cost
Cited by 77
Ben Lippmeier, Manuel M. T. Chakravarty, Gabriele Keller et al. · ACM SIGPLAN Notices · 2012
We present a refined approach to parallel array fusion that uses indexed types to specify the internal representation of each array. Our approach aids the client programmer in reasoning about the performance of their program in terms of the source code. It also makes the intermediate code easier to transform at compile-time, resulting in faster compilation and more reliable runtimes. We demonstrate how our new approach improves both the clarity and performance of several end-user written programs, including a fluid flow solver and an interpolator for volumetric data.
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Siddhartha Chatterjee John, John R. Gilbert · 1993
Data-parallel languages likeFortran 90 express parallelism in the form of operations on data aggregates such as arrays. Misalignment of the operands of an array operation can reduce program performance on a distributed-memory parallel machine by requiring nonlocal data accesses. Determining array alignments that reduce communication is therefore a key issue in compiling such languages.
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Patrick S. Salter, Martin J. Booth · Optics Letters · 2011
Parallel processing in femtosecond-laser-based microfabrication is demonstrated using a microlens array in conjunction with a liquid-crystal spatial light modulator (SLM). A portion of the SLM is mapped onto each individual lenslet in the array and can be used to effectively switch foci on and off for fabrication. In addition, the technique allows for homogenizing the intensity of the array of foci and translating spots relative to their natural focus. The technique demonstrates the potential for high efficiency processing of aperiodic structures.
Cited by 40
Md Abu Hanif Shaikh, G. G. Md. Nawaz Ali, Peter Han Joo Chong et al. · 2016
Success of today's computing depends on finding and operating into data flood with very high number of dimensions. Traditional computing technique for multidimensional data is about half century old and shows worst performance when data dimension is very high. Thus efficient representation and operation on it is cramming needs for data scientist. Two dimensional/row-column representation is facile for imagination and visualization. This paper describes an implementation scheme for higher dimensional array with row-column abstraction on parallel environment like GPU. The representation is just fitting odd dimensions along row-direction and even dimensions along column direction which form groups of 2-D block. Each 2-D block of size blockIdx.x×threadIdx.x is independent of each other. Performance of proposed representation is measured with matrix-matrix addition and multiplication operation. Experimental results show better performance over other representation scheme like Extended Karnaugh Map Representation (EKMR). The scheme can be used for implementing very higher dimensional array in both general purpose and scientific computing on GPU.
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kerblom, Beatrice Ã, Castegren, Elias, Wrigstad, Tobias · arXiv (Cornell University) · 2019
The array is a fundamental data structure that provides an efficient way to store and retrieve non-sparse data contiguous in memory. Arrays are important for the performance of many memory-intensive applications due to the design of modern memory hierarchies: contiguous storage facilitates spatial locality and predictive access patterns which enables prefetching. Operations on large arrays often lend themselves well to parallelisation, such as a fork-join style divide-and-conquer algorithm for sorting. For parallel operations on arrays to be deterministic, data-race freedom must be guaranteed. For operations on arrays of primitive data, data-race freedom is obtained by coordinating accesses so that no two threads operate on the same array indices. This is however not enough for arrays of non-primitives due to aliasing: accesses of separate array elements may return pointers to the same object, or overlapping structures. Reference capabilities have been used successfully in the past to statically guarantee the absence of data-races in object-oriented programs. This paper presents the first extension of reference capabilities -- called array capabilities -- that support concurrent and parallel operations on arrays of both primitive and non-primitive values. In addition to element access, array capabilities support the abstract manipulation of arrays, logical splitting of arrays into subarrays, and merging subarrays. These operations allow expressing a wide range of array use cases. This paper presents the array capability design space and show how it applies to a number of array use cases. The core ideas are formalised and proven sound in a simple calculus, along with a proof that shows that well-typed programs with array capabilities are free from data-races.
Cited by 0Open access
Sheng‐Shian Li, Yu-Wei Lin, Zeying Ren et al. · Proceedings of the IEEE International Frequency Control Symposium · 2007
A method for realizing a high-order on-chip filter response that combines two fourth-order (i.e., two-pole) micro-mechanically-coupled MEMS-based disk-array sub-filters in a parallel configuration has been used to demonstrate a 163-MHz eighth-order (i.e., four-pole) bandpass filter with a 0.16%-bandwidth insertion loss of 2.73 dB, a 20 dB shape factor of only 1.78, and a termination impedance of only 4 kOmega, which is considerably smaller (i.e., better) than that achievable by a parallel combination of single disk resonators. The key to achieving such performance is the use of two capacitively-transduced disk-array composite sub-filters instead of the usual two stand-alone resonators used in previous parallel filter renditions. Here, the use of 275 mum times 360 mum sub-filters, each comprised of coupled radial-contour mode disk arrays, allows a combining of in-phase outputs to substantially raise output currents towards a 50times reduction in motional impedance versus that of a single disk resonator under the same operating conditions. This then lowers the termination impedance required by the overall filter, facilitating the ease with which other components can match to it, and thereby alleviating one of the primary drawbacks of capacitively-transduced micromechanical filters. By utilizing more than 128 disks and mechanical links, the 560 mum x 360 mum filter of this work comprises a true medium-scale integrated (MSI) mechanical circuit on a chip.
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Matthew Felice Pace, Alexander Tiskin · arXiv (Cornell University) · 2013
A deterministic BSP algorithm for constructing the suffix array of a given string is presented, based on a technique which we call accelerated sampling. It runs in optimal O(n/p) local computation and communication, and requires a near optimal O(log log p) synchronisation steps. The algorithm provides an improvement over the synchronisation costs of existing algorithms, and reinforces the importance of the sampling technique.
Cited by 1Open access
Daniel Martelozo Consalter · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2017
Técnicas de aquisição paralelas e hardware dedicados vem sendo desenvolvidos desde a década de 1980 para reduzir o tempo de aquisição de imagens via ressonância magnética (IRM). Uma bobina do tipo phased array é um dispositivo do tipo receptor, que usa múltiplas bobinas (canais) cada qual com seu próprio circuito de detecção para adquirir simultaneamente os sinais que formam uma imagem ou espectro via IRM. Exemplos de técnica de imagem paralela que usa bobinas tipo phased array são Sensitivy Enconding (SENSE) e GeneRalized Autocalibrating Partial Parallel Acquisition (GRAPPA). Sampled array é o nome de um método proposto neste trabalho em que cada canal de uma bobina multicanal é responsável por adquirir de forma independente o sinal da sua amostra de modo que cada sinal de amostra é endereçado ao seu canal específico. Neste trabalho, descrevemos o desenvolvimento de uma bobina phased array de quatro canais para anatomia de cabeça de rato usando circuito impresso flexível para operar em um sistema de IRM pré-clínico de 2T com objetivo de validar o método de construção e uso de circuito flexível como bobina de recepção. Também desenvolvemos uma bobina de quatro canais para realizar simultaneamente a imagem de quatro sementes na mesma varredura para validar o método Sampled Array com objetivo de melhorar a qualidade da imagem e simultaneamente acelerar experimentos de múltiplas amostras. Os resultados mostram que a bobina de circuito impresso phased array, em comparação com uma bobina de enrolamento de fio regular, forneceu uma boa relação sinal / ruído (RSR) e possui geometria mais adequada à anatomia por ser flexível. Além disso, o processo de fabricação da bobina seja facilitado desde que toda a bobina é construída como um protótipo de circuito impresso. Os bons resultados da bobina sampled array mostraram o método como promissor para imageamento de múltiplas amostras com aumento de RSR e diminuição de tempo de experimentos em relação ao uso de bobinas de canal único.
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Roger Cooke, Michiel van Lambalgen · Studia Logica · 1983
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Robert W. Numrich · Lecture notes in computer science · 2006
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Nasa Technical, Nasa Tm · NASA Technical Reports Server (NASA) · 2010
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Amihood Amir, Gad M. Landau · Theoretical Computer Science · 1991
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Paulius Šlevas, Sergej Orlov · Photonics · 2024
We propose a method for creating parallel Bessel-like vortical optical needles with an arbitrary axial intensity distribution via the superposition of different cone-angle Bessel vortices. We analyzed the interplay between the separation of individual optical vortical needles and their respective lengths and introduce a super-Gaussian function as their axial profile. We also analyzed the physical limitations to observe well-separated optical needles, as they are influenced by the mutual interference of the individual beams. To verify our theoretical and numerical results, we generated controllable spatial arrays of individual Bessel beams with various numbers and spatial separations by altering the spectrum of the incoming laser beam via the spatial light modulator. We demonstrate experimentally how to implement such beams using a diffractive mask. The presented method facilitates the creation of diverse spatial intensity distributions in three dimensions, potentially finding applications in specific microfabrication tasks or other contexts. These beams may have benefits in laser material processing applications such as nanochannel machining, glass via production, modification of glass refractive indices, and glass dicing.
Cited by 2Open access