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About 6,839 papers for “Processor array”
Nicolas Maron, T.A. Brengle · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1980
Methods developed to handle bit manipulation on the FPS Array Processor 38-bit main data memory and the problems and successes in converting vector graphics data to raster data are discussed.
Cited by 0
Jesper Vasell, Jonas Vasell, Jonas Vasell et al. · Future Generation Computer Systems · 1992
Cited by 7
Edson dos Santos Moreira, Richard Zobel · 2003
An effort was made to design a small and cheap array processing unit (APU) to be used in a major distributed process array processor system for digital signal-processing applications. From the task definition and environment analysis, a design is presented. The unit, based on the Texas TMS 32020 and Intel 80186 is of the load-and-forget type and provides efficient memory management and operand accessing techniques to speed up the processing. An example is provided to illustrate details of the implementation and performance. It is concluded that the design presented fulfils requirements outlined for the APU.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0
William Furey, B. C. Wang, M. Sax · Acta Crystallographica Section A Foundations of Crystallography · 1981
The paper will give an introductory survey on the use of microprocessors in crystallographic instrumentation and computing facilities. It
Cited by 0Open access
T Bugir, A Cantoni · UWA Profiles and Research Repository (University of Western Australia) · 1983
Cited by 0
J.G. McWirter, T.J. Shepherd · 1990
The authors describe a novel systolic array which can efficiently compute the minimum variance distortionless response (MVDR) from an array of antenna receiver elements in a rapidly changing signal environment. The MVDR beamforming problem amounts to minimising, in a least squares sense, the combined output from an antenna array subject to K independent linear equality constraints each of which corresponds to a chosen 'look direction' The constraints are independent in the sense that, for each new vector of received data samples, it is necessary to compute the minimum array output subject to each constraint in turn. This involves the solution of K independent, but closely related, least squares minimisation problems.
Cited by 1
F Smith Barry, Nikos Pitsianis, G.G. Pechanek et al. · Computer engineering series · 2007
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Laseena C. A · International Journal of Engineering Research and · 2016
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Jay Zagorsky · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983
Matrix operations are the basic building blocks of many graphic operations. Rotating or scaling a three dimensional scene is easily accomplished by changing the point matrix that defines the picture. To operate in real time, however, a graphics program must be able to change the point matrix as fast as the display can be refreshed. In the step-wise refinement presented four methods of performing three dimensional transformations are described. The first two, which use FORTRAN code only, work in real time-but for a limited number of cases. The last two, which use the Skymnk array processor, perform three dimensional transformations at real time speed in all cases.
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D. C. Rapaport · Computer Physics Communications · 1985
Cited by 1
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov et al. · 2006
In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost. The applicability of our approach is tested in a case study with different interconnect topologies on an FPGA platform. The results show substantial flexibility gains with only marginal additional hardware cost
Cited by 77
Philip A. Marks · Computer Graphics and Image Processing · 1980
Cited by 28
Swigert, D. · USRA Houston Repository (Lunar and Planetary Institute) · 2017
Demand matrix -- Interface card -- Timing and control word generator -- Sequencer module specification -- A/D converter module specification -- Signal conditioner card specification.
Cited by 0
Foster, H.J., Leeds Univ. (UK). Dept. of Computer Studies · OpenGrey (Institut de l'Information Scientifique et Technique)
Cited by 0
Zhiquan Guo, Jungang Han, Tao Li · 2015
This paper presents an implementation of OpenVX on the PAAG array processor (Polymorphic Array Architecture for Graphics and image processing), which is a novel polymorphous architecture designed for graphics rendering and image processing. OpenVX is a new standard for implementing and optimizing low-level image processing and computer vision released by Khronos. It uses a graph-based execution model to combine function enabling both task and data-independent execution. We propose two OpenVX graph mapping modes for PAAG: Whole Graph Mapping (WGM) and Single Node Mapping (SNM). Experimental results indicate that the two modes are both effective, but WGM is better that SNM in terms of efficiency, the experiments also illustrates PAAG has a great potential on image processing and computer vision on array processor.
Cited by 2
Roberts, Magotra · 1989
Some details are presented of a VLSI (1.2- mu m CMOS) digital array signal processor (DASP) which has been designed for applications in high-performance fast Fourier transform (FFT)-based digital signal processing systems. The processor chip performs about 500 million arithmetic operations per second and operates at an input/output (I/O) rate of 5 billion bits per second. The controller chip provides total system control for FFT-based DSP systems. FFT-based algorithms such as spectrum analysis and digital filtering (via frequency domain) can be defined on the chip set by coding five to ten instructions in the controller. Although a single chip set can process data rates at very high speeds (e.g. IK FFT in 61 mu s), multiple stages can be cascaded very simply for extremely high performance (up to 100 MHz data rates). The DASP and its controller, the programmable array controller (PAC), are packaged separately in 269 pin PGA and 180 pin PGA packages, respectively, and each chip dissipates about 2.0 W. The DASP performs all of its operation in fixed-point or block floating-point arithmetic, and a brief analysis of the quantization errors introduced by the device is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 2
Chan Choong Wah · 2002
The design of a matrix arithmetic processor using the Gould CMOS 2-μm gate array design kit is described. The background leading to the formulation of the matrix arithmetic processor is presented, along with its design, implementation, simulation and analysis. A 16-bit floating-point format is proposed.
Cited by 0
Mehdi Safarpour, Ilkka Hautala, Miguel Bordallo López et al. · University of Oulu Repository (University of Oulu) · 2019
Cited by 5
B E Khaĭkin, F M Shaverdyan · Soviet Journal of Quantum Electronics · 1975
An analysis is made of the possibility of realization of two-dimensional shift operation in an optical array processor by the location of diffraction gratings in the spectral plane. Relationships describing the shift operation are derived.
Cited by 0
Raymond J. Lackey, Herbert F. Baurle, John Barile · 2003
A systolic processor applicable to a general class of signal processing problems was built using commercially available VLSI floating-point processors. This processor performed over 1.25 BFLOPS (billion floating-point operations per second) in applications of solutions to a group of simultaneous equations with 12 unknowns. The solution was designed to work with the normal equations used in signal processing problems where all equations have noisy component values. The processor design was a direct implementation of algorithm mathematics in hardware and achieved a high processing rate through extensive concurrency. This program demonstrated how a custom, application-specific processor can be developed in less than two years to perform a computationally intensive function.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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