D.G. Hart, A.A. Girgis · 2002
The paper presents the implementation of the Kalman filtering algorithm on a Zoran ZR34161 vector signal processor (VSP). The VSP is a microprocessor that is designed to manage mathematical operations on complex arrays (vectors) of data. Thus, the VSP is able to manipulate vectors of real or complex data as easily as conventional microprocessors can manipulate a single element of data. The vector format of the VSP makes the processor ideal for various filtering applications. Kalman filtering is a discrete optimal estimator that has found a wide variety of applications and is the method employed in this paper.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 3
Basil Sh. Mahmood, Mamoon A. Al Jbaar · 2011
This paper handle the design and implementation of the SIMD Vector Processor on FPGA, this processor consist of 4 parallel lanes (processing elements PEs) that work simultaneously independent with each other, each one of those lanes has its own arithmetic units, vector register file which represents a part of the main distributed register file also it has a local memory for storage of execution results of that lane, lanes's local memories connects to each other to exchange their contains via interconnection networking that can be configure software to give a certain topology of static interconnection network, like (Mesh, Star,...etc) those lanes and their memories act a vector part of the SIMD Vector Processor. A scalar processor also designed and attached with the vector part in order to accomplish scalar instructions that can not be handle by vector lanes, this processor also has its scalar register file and set of arithmetic units.
Cited by 10
Greg Faanes, Ground Rules For The Design, Sv Chipset · 1998
Overview: • Goals and ground rules for the design • CPU/Cache overview • CPU chip • Scalar unit design • Vector unit design • Streaming cache chip • Cache unit design
Cited by 0
Silviu Ciricescu, Ray Essick, Brian Lucas et al. · 2007
The need to process multimedia data places large computational demands on portable/embedded devices. These multimedia functions share common characteristics: they are computationally intensive and data-streaming, performing the same operation(s) on many data elements. The Reconfigurable Streaming Vector Processor (RSVP ) is a vector coprocessor architecture that accelerates streaming data operations. Programming the RSVP architecture involves describing the shape and location of vector streams in memory and describing computations as data-flow graphs. These descriptions are intuitive and independent of each other, making the RSVP architecture easy to program. They are also machine independent, allowing binary-compatible implementations with varying cost-performance tradeoffs. This paper presents the RSVP architecture and programming model, a programming case study, and our first implementation. Our results show significant speedups on streaming data functions. Speedups for kernels and applications range from 2 to over 20 times that of an ARM9 host processor alone.
Cited by 0
M. Johns, Tom J. Kázmierski · 2020
This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V `V' extension for vectors, part of the open-source RISC-V instruction set architecture (ISA). Being aimed at small embedded devices, it demonstrates a simpler method of parallel execution than traditional vector architectures to minimise logic. It has been synthesised for testing on an FPGA at 50MHz. Typical vector-compatible applications have been used as benchmarks. Performance has been improved by up to 5.8x for the demonstrated applications relative to a comparable scalar RISC-V processor, for an increase in FPGA resource utilisation of at most 2.6x.
Cited by 42
Seyed A. Rooholamin, Sotirios G. Ziavras · Microprocessors and Microsystems · 2015
Cited by 8
K.J. Balakrishnan, Nur A. Touba · 2003
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processor's on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.
Cited by 16
SeyedAmin Rooholamin · 2016
Cited by 0
E.R. Prado, J.P. Prewitt · 2002
A scalable, re-programmable radiation hardened vector processor for space applications is presented. An architectural approach combining a vector processor and a general purpose digital signal processor is shown to yield substantial processing gains over traditional implementations. Point solutions are presented yielding savings of up to five times the size, weight, and power over traditional implementations.
Cited by 3
Timothy Hayes · QRU Quaderns de Recerca en Urbanisme · 2011
English: This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64\n\t\t\t\t microprocessors using true vector ISA extensions. First, a state of art DSS database management\n\t\t\t\t system (DBMS) is pro led and bottlenecks are identi ed. From this, the bottlenecked\n\t\t\t\t functions are analysed for data-level parallelism and a discussion is given as to why the existing\n\t\t\t\t multimedia SIMD extensions (SSE) are not suitable for capturing this parallelism. A vector ISA\n\t\t\t\t is derived from what is found to be necessary in these functions; additionally, a complementary\n\t\t\t\t microarchitecture is proposed that draws on prior research done in vector microprocessors but\n\t\t\t\t is also optimised for the properties found in the pro led application. Finally, the ISA and microarchitecture\n\t\t\t\t are implemented and evaluated using a cycle-accurate x86-64 microarchitecture\n\t\t\t\t simulator.
Cited by 0Open access
N. Mading, J. Leenstra, J. Pille et al. · 2005
A vector fixed point unit (FXU) is designed to speed up multimedia processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology.
Cited by 6
N. Mading, J. Leenstra, J. Pille et al. · 2006
A vector fixed point unit (FXU) is designed to speed up multi-media processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology
Cited by 5
Николай Иванович Дикарев, B. M. Shabanov, Александр Сергеевич Шмелёв · Program systems theory and applications · 2020
Статья посвящена анализу выполнения программы быстрой сортировки (QS) в векторном процессоре с архитектурой управления потоком данных, в котором для хранения массивов используется метод векторов/указателей. Анализируется выявленный на программе QS недостаток хранения массивов с помощью векторов указателей и предложен способ решения этого недостатка введением команд split и fuse в систему команд процессора. Несмотря на значительное усложнение графа и числа выполняемых команд в программе QS, введение в систему команд ВПП новых команд split и fuse позволило достичь на этой программе до 11 раз более высокой производительности по сравнению с процессорным ядром Intel Skylake. Причем пиковые производительности ВПП и Intel Skylake различаются в 8 раз.
Cited by 1Open access
Николай Иванович Дикарев, B. M. Shabanov, Александр Сергеевич Шмелёв · Program systems theory and applications · 2021
Статья посвящена анализу выполнения программы быстрой сортировки (Quicksort) в векторном процессоре с архитектурой управления потоком данных (ВПП), в котором для хранения массивов используется метод векторов/̄указателей. Выявленный ранее на программе Quicksort недостаток хранения массивов с помощью векторов указателей был компенсирован введением команд split и fuse в систему команд процессора. Анализируется усовершенствованный граф программы Quicksort и результаты её моделирования на исходной и модернизированной системе команд ВПП. Производится сравнение результатов моделирования ВПП с производительностью процессорного ядра IntelSkylake.
Cited by 1Open access
Yoshiyuki Kido, Sosuke Kamisako, Y. Tamada et al. · 2025
INGOR infers gene regulatory networks using Bayesian networks, preceded by multivariate preprocessing such as normalization, imputation, and correlation analysis. The computational cost grows exponentially with gene count, causal combinations, and sample size, making acceleration essential. This study investigates vector processor acceleration for INGOR by profiling bottlenecks and integrating optimized numerical libraries. Performance was evaluated using a dataset of 10,540 genes and 500 samples, comparing execution times and function-level vectorization rates between CPU and vector-accelerated implementations.
Cited by 0
Rahimi Kari, Sadra · D-Scholarship@Pitt (University of Pittsburgh) · 2024
Recent advancements in artificial intelligence (AI) have hinged on the capacity to train increasingly vast parameter sets within neural networks, a trend that has outpaced the computational capabilities of traditional digital hardware. This has led to a critical need for new computing paradigms that can simultaneously enhance computational efficiency and throughput. Photonic analog computing emerges as a promising solution to reduce latency and boost performance, particularly in addressing the memory-related challenges that underpin AI's success. This thesis presents an overview of the integration of optical and electrical memories with photonic hardware, underlining the pivotal role of memory technologies. It emphasizes the need for more efficient and compact memory for optical computing and presents an integrated coherent solution to process temporally multiplexed optical signals using a modular dot-product unit cell. We use these unit cells to demonstrate multiply accumulate operations on real- and complex-valued inputs using coherent detection and temporal integration. We then extend this to computing the covariance between stochastic bit streams which can be used to estimate correlation between data streams in the optical domain. Finally, we demonstrate a path to scaling up our platform to enable general matrix-matrix operations. This approach has the potential to enable highly efficient and scalable optical computing on-chip for a broad variety of AI applications.
Cited by 0
An Balakrishnan Van, B. Juurlink S. Vassiliadis · 2007
Multimedia applications provide new highly valuable services to the consumer and form, consequently, a new important workload for desktop systems. The increased computing power of the embedded processors required in baseband processing for new high-bandwidth wireless communication protocols (e.g UMTS, CDMA2000) can make multimedia processing possible also for the mobile devices, such as cell phones. These devices must meet high performance requirements of multimedia applications while maintaining low cost and low power consumption. As a new platform which can provide the necessary computing power for processing the inner tranciever functions of the modem for UMTS, Philips develops a novel processor, called Co Vector-Processor (CVP), which is based on the following techniques. First, CVP exploits the datalevel parallelism (DLP) by processing 256-bit data items, which are interpreted as vectors consisting of 32 8-bit, 16 16-bit, or eight 32-bit elements. Therefore, a single vector instruction of CVP performs up to 32 operations. Second, CVP also exploits the instruction-level parallelism (ILP) using VLIW approach: several vector instructions are packed in a single very long instruction word (VLIW), and are executed in parallel.
Cited by 0
Tang, Rui, Okano, Makoto, Zhang, Chao et al. · Figshare · 2025
The slowing down of Moore's law has driven the development of application-specific processors for deep learning. Analog photonic processors offer a promising solution for accelerating matrix-vector multiplications (MVMs) in deep learning by leveraging parallel computations in the optical domain. Intensity-based photonic MVM processors, which do not utilize the phase information of light, are appealing due to their simplified operations. However, existing intensity-based schemes for such processors often employ wavelength multiplexing or mode multiplexing, both of which have limited scalability due to high insertion loss or wavelength crosstalk. In this work, we present a scalable intensity-based photonic MVM processor based on the concept of waveguide multiplexing. This scheme employs multiport photodetectors (PDs) to sum the intensities of multiple optical signals, eliminating the need for multiple wavelengths or modes. A 16-port Ge PD with a 3 dB bandwidth of 11.8 GHz at a bias voltage of -3 V is demonstrated, and it can be further scaled up to handle 250 ports while maintaining a 6.1 GHz operation bandwidth. A 4×4 circuit fabricated on a Si-on-insulator (SOI) platform is used to perform MVMs in a 3-layer neural network designed for classifying Iris flowers, achieving a classification accuracy of 93.3%. Furthermore, the performance of large-scale circuits in a convolutional neural network (CNN) for Fashion-MNIST is simulated, resulting in a classification accuracy of 90.53%. This work provides a simplified and scalable approach to photonic MVM, laying a foundation for large-scale and multi-dimensional photonic matrix-matrix multiplication in optical neural networks.
Cited by 0Open access
Tang, Rui, Okano, Makoto, Zhang, Chao et al. · Figshare · 2025
The slowing down of Moore's law has driven the development of application-specific processors for deep learning. Analog photonic processors offer a promising solution for accelerating matrix-vector multiplications (MVMs) in deep learning by leveraging parallel computations in the optical domain. Intensity-based photonic MVM processors, which do not utilize the phase information of light, are appealing due to their simplified operations. However, existing intensity-based schemes for such processors often employ wavelength multiplexing or mode multiplexing, both of which have limited scalability due to high insertion loss or wavelength crosstalk. In this work, we present a scalable intensity-based photonic MVM processor based on the concept of waveguide multiplexing. This scheme employs multiport photodetectors (PDs) to sum the intensities of multiple optical signals, eliminating the need for multiple wavelengths or modes. A 16-port Ge PD with a 3 dB bandwidth of 11.8 GHz at a bias voltage of -3 V is demonstrated, and it can be further scaled up to handle 250 ports while maintaining a 6.1 GHz operation bandwidth. A 4×4 circuit fabricated on a Si-on-insulator (SOI) platform is used to perform MVMs in a 3-layer neural network designed for classifying Iris flowers, achieving a classification accuracy of 93.3%. Furthermore, the performance of large-scale circuits in a convolutional neural network (CNN) for Fashion-MNIST is simulated, resulting in a classification accuracy of 90.53%. This work provides a simplified and scalable approach to photonic MVM, laying a foundation for large-scale and multi-dimensional photonic matrix-matrix multiplication in optical neural networks.
Cited by 0Open access
Eugene D. Brooks · Parallel Computing · 1987
Cited by 8