NASA Technical Reports Server (NASA)
Future satellite communications applications will require a packet-switched onboard satellite processing system to route packets at very high speeds from uplink beams to different downlink beams. The rapid emergence of point-to-multipoint services, and the important role of satellites in a national and global information infrastructure, makes the multicast function essential to a fast packet switch (FPS). NASA Lewis Research Center's Digital System Technology Branch has been studying possible architectures for high-speed onboard-processing satellite systems. As part of this research, COMSAT Laboratories developed a broadband integrated services digital network (B-ISDN) fast packet switch for Lewis that was delivered on December 1994. The fast packet switch consists of eight inputs and eight outputs that can receive and transmit data, respectively, at a rate of 155 Mbps. The switch features multiple priorities (three) and multiple-size (three) satellite virtual cells that are similar to ATM cells in length (52 bytes). In addition, the fast packet switch features a congestion-control algorithm that allows users to set different thresholds for individual destination ports, thus throttling back the traffic from the transmitting port.
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Wang T., Yang X., Antichi G. et al. · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 2022
Data-plane programmability is now mainstream. As we find more use cases, deployments need to be able to run multiple packet-processing modules in a single device. These are likely to be developed by independent teams, either within the same organization or from multiple organizations. Therefore, we need isolation mechanisms to ensure that modules on the same device do not interfere with each other. This paper presents Menshen, an extension of the Reconfigurable Match Tables (RMT) pipeline that enforces isolation between different packet-processing modules. Menshen is comprised of a set of lightweight hardware primitives and an extension to the open source P4-16 reference compiler that act in conjunction to meet this goal. We have prototyped Menshen on two FPGA platforms (NetFPGA and Corundum). We show that our design provides isolation, and allows new modules to be loaded without impacting the ones already running. Finally, we demonstrate the feasibility of implementing Menshen on ASICs by using the FreePDK45nm technology library and the Synopsys DC synthesis software, showing that our design meets timing at a 1 GHz clock frequency and needs approximately 6% additional chip area. We have open sourced the code for Menshen's hardware and software at https://isolation.quest/.
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Vic Grout, John Mcginn, John Davies · 2008
The efficiency of packet filters is discussed, that is the effect on processing time of the order of rules in Access Control Lists (ACLs). The problem is introduced and formulated, and various approaches considered. A current optimisation technique is described and potential difficulties noted. A simpler solution, more appropriate for real-time implementation on production routers for example, is then evolved and its implementation discussed.
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Wonmi Choi, Yeonho Yoo, Kyungwoon Lee et al. · IEEE Internet of Things Journal · 2024
This article explores the computing and communication overhead of network processing in Internet of Things (IoT) devices, focusing on containers, a major building block for the edge computing. Our experiments reveal that containers on IoT devices suffer <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.6\times $ </tex-math></inline-formula> higher CPU usage for SoftIRQ processing, ~59% less network throughput, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> higher per-packet latency on average than native processes. While several existing studies enhance networking performance, they often sacrifice interoperability by requiring special hardware or modifying networking semantics or APIs. Thus, we design and implement a kernel networking accelerator, called SCON, that maintains interoperability, crucial for IoT devices. SCON addresses major bottlenecks in container networking through system-level profiling. We evaluate SCON with three types of IoT devices. On the Raspberry Pi 4, SCON reduces the latencies of major IoT application protocols (e.g., HTTP and MQTT) by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10\times $ </tex-math></inline-formula>, achieving a similar level of latency to the native process. Further analysis shows that SCON reduces CPU usage for SoftIRQ processing by ~26%. We also report similar improvements on the other two IoT devices. Our conclusion is that SCON is unique in significantly reducing the computing and communication overhead of container networking in IoT devices while maintaining interoperability. Furthermore, it works consistently across different types of devices, whether wired or wireless, and regardless of heavy or sporadic traffic.
Cited by 2
Hamid Ghasemirahni, Alireza Farshin, Mariano Scazzariello et al. · Proceedings of the ACM on Networking · 2024
Data centers increasingly utilize commodity servers to deploy low-latency Network Functions (NFs). However, the emergence of multi-hundred-gigabit-per-second network interface cards (NICs) has drastically increased the performance expected from commodity servers. Additionally, recently introduced systems that store packet payloads in temporary off-CPU locations (e.g., programmable switches, NICs, and RDMA servers) further increase the load on NF servers, making packet processing even more challenging. This paper demonstrates existing bottlenecks and challenges of state-of-the-art stateful packet processing frameworks and proposes a system, called FAJITA, to tackle these challenges & accelerate stateful packet processing on commodity hardware. FAJITA proposes an optimized processing pipeline for stateful network functions to minimize memory accesses and overcome the overheads of accessing shared data structures while ensuring efficient batch processing at every stage of the pipeline. Furthermore, FAJITA provides a performant architecture to deploy high-performance network functions service chains containing stateful elements with different state granularities. FAJITA improves the throughput and latency of high-speed stateful network functions by ~2.43x compared to the most performant state-of-the-art solutions, enabling commodity hardware to process up to ~178 Million 64-B packets per second (pps) using 16 cores.
Cited by 4Open access
Hayato Yamaki · International Journal of Communication Systems · 2020
Summary Owing to the explosive increase in Internet traffic, increasing the throughput and energy efficiency of core routers is an important issue for future internet. Accessing the ternary content addressable memory (TCAM) in a core router can significantly degrade its throughput and energy efficiency owing to its low operating frequency and power consuming operations. To improve the throughput and energy‐efficiency of core routers, packet processing caches (PPCs) can be potentially used. PPCs can reduce the number of TCAM accesses by storing the TCAM lookup results in a fast and low‐energy cache memory and reusing them to process subsequent packets. To enhance the PPC performance, it is important to reduce the number of PPC misses. However, the PPC miss rate of the state‐of‐the‐art PPC is still high owing to its small capacity. In this study, we propose an effective cache replacement policy, called elevator cache (ELC) to improve the PPC miss rate. Our simulation results showed that the 8‐way ELC, which can be implementable at low hardware cost, reduced the number of PPC misses by 17.1% and 5.67% in comparison to the 4‐way least recently used (LRU) and the 4‐way ELC, respectively. Consequently, it was found that the 8‐way ELC can achieve a 1.21 times higher throughput (560 Gbps) while consuming 83% energy in comparison to conventional PPCs.
Cited by 2
A. Yokoyama · IEICE Transactions on Communications · 2005
In this paper we propose a new reconfigurable signal processing platform for SDR, having capability to change its processing parameters dynamically. On our proposed platform, while the wiring and processing scheme remain fixed, processing parameters and connections between processing modules together with the associated dataflow can be changed. We also demonstrate that our proposed signal processing platform has the new ability of easily composing new signal processing models dynamically, simultaneously with other tasks, and attaining high efficiency of logic usage.
Cited by 1
Patrick Eugster, Kirill Kogan, Sergey Nikolenko et al. · 2014
Packet processing increasingly involves heterogeneous requirements. We consider the well-known model of a shared memory switch with bounded-size buffer and generalize it in two directions. First, we consider unit-sized packets labeled with an output port and a processing requirement (i.e., packets with heterogeneous processing), maximizing the number of transmitted packets. We analyze the performance of buffer management policies under various characteristics via competitive analysis that provides uniform guarantees across traffic patterns (Borodin and El-Yaniv, 1998). We propose the Longest-Work-Drop policy and show that it is at most 2-competitive and at least sqrt 2}-competitive. Second, we consider another generalization, posed as an open problem in [10], where each unit-sized packet is labeled with an output port and intrinsic value, and the goal is to maximize the total value of transmitted packets. We show first results in this direction and define a scheduling policy that, as we conjecture, may achieve constant competitive ratio. We also present a comprehensive simulation study that validates our results.
Cited by 21
Tsiamoura, Konstantina · TU München - Informatik · 2014
Cited by 4Open access
Xiangyu Gao, Taegyun Kim, Aatish Kishan Varma et al. · 2019
Packet-processing code should be fast. But, it is hard to write fast code for programmable substrates such as high-speed switches, multicore SoC SmarfNICs, FP-GAs, middleboxes, and the end-host stack. Today, expert developers with deep familiarity with the underlying hardware handcraft such code. Making things worse, building optimizing compilers for these substrates requires significant development effort, which may not be available for these new, niche, and evolving substrates.
Cited by 16
Dániel Horváth, Imre Bertalan, István Moldován et al. · Lecture notes in computer science · 2010
Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modeling environment, where the new application is modeled in SystemC. Furthermore, our power management is modeled and tested against different traffic loads through extensive simulation analysis. Our results show that our proposed solution can help to reduce the energy consumption significantly in a wide range of traffic scenarios.
Cited by 2Open access
D. Cotter, M.C. Tatham, Julian Lucek et al. · 1997
Cited by 10
Olsson, Josef, Stenström, Isak · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2023
When building a packet processing system, it is common to use frameworks that are written in C and built upon DPDK Eventdev, which is what Ericsson AB currently uses. However, using Rust async for this task could improve the developer experience and efficiency. This thesis explores the use of Rust async for creating reliable packet processing systems by implementing Rust Packet Processing Performance Prototype (RPPPP), which uses the Rust async runtime Glommio. RPPPP was implemented with support for using both centralized and decentralized scheduling. Two applications, that closely mirror the functionality of two existing DPDK Eventdev programs, were developed using RPPPP. One of the existing programs is a public DPDK Eventdev example application that uses a centralized scheduler, and the other is an internal Ericsson benchmarking application that uses a decentralized scheduler. The performance of DPDK and RPPPP was compared by evaluating the performance of all four applications for different core counts. The results show that the Rust application with the decentralized scheduler has a throughput that is between 20% and 50% of its DPDK counterpart, while its latency is far worse. The Rust application with a centralized scheduler performs significantly worse than any of the other applications when using more than 4 cores, both in terms of throughput and latency, but this is deemed to not be the true potential of the performance of this approach. Though not fully conclusive, the result of this thesis indicates that using Rust async for packet processing systems is currently not a viable approach.
Cited by 0Open access
Muhammad Kashif Khattak, Hamza Fahim, Muhammad Faran Majeed et al. · IEEE Systems Journal · 2020
The network switches and routers need to forward the network packets at a line-rate. The underlying hardware and software implementations may limit the performance of these packet processing devices. In this paper, we propose a novel model, called Lookaside, to increase the performance of the network switches by extracting the payload from the packet and storing it in a nearby standard memory, such as dynamic random access memory (DRAM), before the packet is sent for processing. We know that the packet payload has no role in packet processing. We implemented the prototypes of our Lookaside switch model on the state-of-the-art ONetSwitch45 hardware field-programmable gate array board. The simulation results show an increase in the performance of the switch in terms of latency, throughput, switching chip resources, and on-chip resources power consumption as compared to SimpleSwitch.
Cited by 1
Jayaram Mudigonda, Harrick M. Vin, Lorenzo Alvisi et al. · Texas ScholarWorks (Texas Digital Library) · 2005
First and foremost, I would like to express my gratitude to my thesis supervisor Prof. Harrick Vin. Harrick was instrumental in my building a foundation in the art of critical thinking. He followed through with insightful comments, continually urging me to stay focused and seek out the fundamental wisdom. Harrick’s brilliance, enthusiasm, and his yearning for excellence have inspired me to improve myself throughout my graduate student life. In addition to helping me with my academic matters, Harrick has been a well-wisher, a true friend and a guide; a lot of what I learnt about life in general is due to him. I would like to express my heartfelt thanks to Prof. Steve Keckler. Steve helped me with many technical problems that I would not have been able to get past on my own. He has been unfailingly kind to me and was always willing to teach me in spite of my innate petulance. Without Steve’s generous help, I would not have been able to finish this dissertation. I would also like to thank Dr. Raj Yavtkar of Intel Corporation. Raj was instrumental in initiating the work that eventually grew into my thesis. Raj’s extraordinary ability to strike the right balance between
Cited by 0Open access
Jayaram Mudigonda · 2005
Abstract: In this study, we refute the popular belief [1, 2] that packet processing does not benefit from data-caching. We show that a small data-cache of 8KB can bring down the packet processing time by much as 50-90%, while reducing the off-chip memory bandwidth usage by about 60-95%. We also show that, unlike general-purpose computing, packet processing, due to its memoryintensive nature, cannot rely exclusively on data-caching to eliminate the memory bottleneck completely.
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Brunella M. S., Belocchi G., Bonola M. et al. · Cineca Institutional Research Information System (Tor Vergata University) · 2020
FPGA accelerators on the NIC enable the offloading of expensive packet processing tasks from the CPU. However, FPGAs have limited resources that may need to be shared among diverse applications, and programming them is difficult. We present a solution to run Linux's eXpress Data Path programs written in eBPF on FPGAs, using only a fraction of the available hardware resources while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized or completely removed, when targeting a purpose-built FPGA executor, thereby significantly improving performance. We leverage that to design hXDP, which includes (i) an optimizing-compiler that parallelizes and translates eBPF bytecode to an extended eBPF Instruction-set Architecture defined by us; a (ii) soft-CPU to execute such instructions on FPGA; and (iii) an FPGA-based infrastructure to provide XDP's maps and helper functions as defined within the Linux kernel. We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation is clocked at 156.25MHz, uses about 15% of the FPGA resources, and can run dynamically loaded programs. Despite these modest requirements, it achieves the packet processing throughput of a high-end CPU core and provides a 10x lower packet forwarding latency.
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Rare & Special e-Zone (The Hong Kong University of Science and Technology) · 2013
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2008
Abstract—The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, they are hard to be effectively utilized because of the explicit data movement between different memory levels. However, traditional cache also cannot be directly incorporated into NP because of its low efficiency in locality exploitation under network environment. In this paper, a novel memory hierarchy component, called split control cache, is presented. The proposed scheme employs two independent low latency memory stores to temporarily hold the flow-based and application-relevant information, exploiting the different locality behaviors exhibited by these two types of data. Just like conventional cache, data movement is manipulated by specially designed hardware to release the programmer from details of memory management. Performance evaluation shows that this component can achieve a hit rate of over 90 % with only 16 KB of memories in route lookup implementations for link rate of OC-3 and provide enough flexibility for the implementation of most network applications. Index Terms — Cache, high speed processing, memory architecture, network processor. I.
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Wangyang Lai, Chin‐Tau Lea · IEEE Micro · 2003
The Internet is expanding rapidly and constantly adding new protocols and features. To shorten the design cycle, many companies have adopted a common hardware platform for a variety of products. In these products, specialized packet processors tailored for packet processing handle multiple protocols and feature changes. A packet processor usually incorporates multiple RISC engines that are configurable as several instances of parallel processors, working simultaneously or in a pipelined fashion. In either approach, packet processors are complex and expensive. Packet processing has many levels of programmability requirements. Some tasks require only mild programmability and can't justify the use of a full-fledged packet processor. A finite scare machine (FSM), on the other hand, has high performance but cannot adapt to protocol changes. The solution is something in between: fast, programmable, but not as complicated as a packet processor. A programmable state machine (PSM) is such an idea.
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