Xiaoli Li, Jianhe Du, Jianguo Hu et al. · 2015
At present, parallel signal processing tasks is applied more and more widely. Traditional way of development of parallel signal processing tasks is custom development. This development way needs manual programming, the development cycle is long, and the platform portability is poor. The parallel signal processing software discussed in this paper will make revolutionary change in the way of development of parallel signal processing tasks. The goal of parallel signal processing tasks is to achieve fully graphical and modularized development under an integrated development software environment. The software can automatically generate codes. Besides, the software provides the function of predicting and evaluating the performance. Furthermore, the software has generalization of hardware platform. c 2015 Taylor a Francis Group, London.
Cited by 1
S. Levialdi · 1985
Cited by 3
Charles Weems, Edward M. Riseman, Andrew J. Hanson et al. · 2003
A benchmark is presented that was designed to evaluate the merits of various parallel architectures as applied to image understanding (IU). This benchmark exercise addresses the issue of system performance on an integrated set of tasks, where the task interactions that are typical of complex vision application are present. The goal of this exercise is to gain a better understanding of vision architecture requirements, which can be used to guide the development of the next generation of vision architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 5
Marc D. Binder, Nobutaka Hirokawa, Uwe Windhorst · 2008
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C.A.R. Hoare · Oxford University Research Archive (ORA) (University of Oxford) · 2015
Cited by 0Open access
Deo,Narsingh · Defense Technical Information Center (DTIC) · 1986
Recent advancements in hardware technology have made it attractive to use many processors in parallel that cooperate and coordinate their efforts to solve a problem much faster. Such parallel computers are currently being developed, designed and experimented with. A few, with limited parallelism, are available as commerical products, such as, Intel's iPSC, NCUBE, Sequent's Balance 8000 and 21000. It appears certain that computers are going to be in wide use in 1990's. However, the art of designing parallel algorithms is far behind that of sequential algorithms. The goal of this project was to develop strategies for designing parallel algorithms and computer programs for a certain class of problems consisted of various graph problems that arise on large, sparse, real-life transportation and communication networks. The parallel computer deemed most suited for such problems is a multiple-instruction, multiple-data stream (MIMD) machine.
Cited by 0
Sing H. Lee · Defense Technical Information Center (DTIC) · 1986
Optical computing has been effective at solving computationally difficult problems. Optical computing research has high risk, but high potential benefits. AFOR has had the lead role in basic optical computing research and must continue this role in coordination with other government and industrial funding. Current and future optical computing systems can be organized into a unified structure with five major components: input, processor array, interconnections, memory, output. Optics has great potential advantages in speed, bandwidth and parallelism, but electronics has the advantages of a well-developed technology. Basic research needs:-Materials - nonlinear, synthetic structures, processing element arrays - SMLs, interconnections/memories - materials, devices, arrays, architectures/algorithms - utilize parallelism.
Cited by 0
S. Freitas · 4th International Congress of the Brazilian Geophysical Society · 1995
Different types of parallel architectures present different types of trade-offs for the users. In this paper we will review common problems in implementing and using these systems and present our practical experience for solving them.
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Takahira Yamaguchi, Yoshikazu Tezuka, Osamu Kakusho · 1985
In this paper, Parallel Resolution Algorithm (PARA) is described to improve the execution efficiency in resolution process. PARA consists of two parts: parallel unification and generation of a resolvent. The first part is characteristic of PARA, which partitions whole set of expressions W into independent clusters as pre-processing and unifies each cluster in parallel. The efficient implementation for the processing peculiar to PARA is presented and checked by means of the experiment in comparison of execution efficiency of resolution. Experimental results show PARA is very effective in occurrence of many clusters.
Cited by 3
Leoncini, Mauro · IRIS UNIMORE (University of Modena and Reggio Emilia) · 1992
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T. Kawabata, N. Sashida, Y. Yamamoto et al. · IEEE Transactions on Power Electronics · 1991
A novel method of instantaneous voltage and power balance control of a parallel processing inverter system is proposed. It consists of a high-speed switching PWM (pulsewidth modulated) inverter with an instantaneous current minor loop controller, a voltage major loop controller, and a power balance controller. This system realizes the following functions with only one inverter: constant AC output voltage control with reactive power control, active filtering to absorb load current harmonics, DC voltage and current control as AC-to-DC converter, and uninterruptible power supply (UPS) for stand-alone operation. This system covers a wide application range, including UPS systems, new energy systems, and active filters with voltage control functions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 66
Y. Wallach · Lecture notes in computer science · 1982
Cited by 46
Tony Hoare · 1993
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Gordon Lyon · 1987
This is a summary of preliminary work and experiences at NBS on benchmarks for parallel machines. Discussion covers the several roles that benchmarks play, ideal and realistic settings, and quick reviews of several types of benchmark sets. Several conclusions can be drawn, given the rudimentary nature of parallel processor characterization: (i) That the performance metrics be embedded in more comprehensive frameworks that can be appraised and modified as needed; (ii) That one universal framework is beyond reach, since distinct clusters of use are emerging with separate emphases; (iii) That large application benchmarks are most successf^ul when they run well on a machine, and thereby demonstrate compatibility of job and architecture; (iv) That the value of smaller metrics (fragments of code) is more diagnostic and preventive than predictive; small metric sets should encourage the parametric study of architectures and applications, and thus promote both economical hardware enhancement and suitable program design.
Cited by 8Open access
Comfort, John C., Jefferson, David, Reddy, Y. V. et al. · NCSU Libraries Repository (North Carolina State University Libraries) · 2012
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Virginio Cantoni, L. Carrioli, Marco Ferretti et al. · 1986
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Ecker, K., Hirschberg, R. (eds.), Technische Univ. Clausthal, Clausthal-Zellerfeld (Germany). Inst. fuer Informatik · OpenGrey (Institut de l'Information Scientifique et Technique) · 1992
Available from TIB Hannover: RO 7834(1993,5) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische Informationsbibliothek
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Amestoy PR, Berger P, Daydé MJ et al. · Science and Technology Facilities Council · 1999
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Bots, LH · TU/e Research Portal (Eindhoven University of Technology) · 1983
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NONE · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2013
This report contains viewgraphs from the Special Parallel Processing Workshop. These viewgraphs deal with topics such as parallel processing performance, message passing, queue structure, and other basic concept detailing with parallel processing.
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