Hiroshi Nakamura, H. Imori, Yoshiyuki Yamashita et al. · 1994
We present a new scalar processor for high-speed vector processing and its evaluation. The proposed processor can hide long main memory access latency by introducing slide-windowed floating-point registers with data preloading feature and pipelined memory. Owing to the slide-window structure, the proposed processor can utilize more floating-point registers in keeping upward compatibility with existing scalar architecture. We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed processor drastically reduces the penalty of main memory access compared with an ordinary scalar processor. For example, the proposed processor with 96 registers hides memory access latency of 70 CPU cycles when the throughput of main memory is 8 byte/cycle. From these results, it is concluded that the proposed architecture is very suitable for high-speed vector processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 8
Grant Davidson, T. Stanhope, R. Aravind et al. · 2005
Vector Quantization is an attractive block coding scheme which allows more efficient use of a given channel capacity. The computational complexity of the codebook search, however, limits the practical applications of Vector Quantization -- especially in real-time situations. This paper presents a special purpose processing architecture which supports real-time search of large codebooks. The core of the computation required for a squared-error distortion measure is accomplished using a VLSI pattern matching chip. We describe a pipeline architecture which reduces the effective computation time for a single vector component to one period. The chip supports a selectable vector dimension of 2, 4, 8, or 8 and can be used with any codebook size consistent with the input vector rate and the chip's throughput. We have built and tested a 4-micron NMOS chip which supports up to four million squared-error distance calculations per second. We outline three approaches to real-time Vector quantization which use this chip to do the pattern matching: two waveform coding processors using Vector Pulse Code Modulation and Adaptive Vector Predictive Coding, and a novel approach to rapid codebook design.
Cited by 10
Guillem Cabo, Gerard Candón, Xavier Carril et al. · UPCommons institutional repository (Universitat Politècnica de Catalunya) · 2022
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.
Cited by 6Open access
Kim Rounioja, et al. · 2006
SIMD paradigm enhances cost and power efficiency of instruction set processors when the executed workload contains appropriate data level parallelism. In this paper, we investigate development of a SIMD ASIP for an HSDPA equalizer receiver for mobile handsets. The ASIP is based on a vector processor template with C-based programming interface. The template is enhanced to capture the 14.4Mbps HSDPA equalizer receiver functionality of the wireless modem. The solution provides improved flexibility compared to the conventional approach while requiring only modest design effort. The template and the design approach can be utilized also for other subsets of modem baseband.
Cited by 0
Michael R. Feldman, Clark C. Guest · 1989
We have noted an error in our original paper. 1 Equation (5) should read as
Cited by 0
Junyang Zhang, Yang Guo, Xiao Hu · Advances in intelligent systems and computing · 2017
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Tang, Rui, Okano, Makoto, Zhang, Chao et al. · Figshare · 2025
The slowing down of Moore's law has driven the development of application-specific processors for deep learning. Analog photonic processors offer a promising solution for accelerating matrix-vector multiplications (MVMs) in deep learning by leveraging parallel computations in the optical domain. Intensity-based photonic MVM processors, which do not utilize the phase information of light, are appealing due to their simplified operations. However, existing intensity-based schemes for such processors often employ wavelength multiplexing or mode multiplexing, both of which have limited scalability due to high insertion loss or wavelength crosstalk. In this work, we present a scalable intensity-based photonic MVM processor based on the concept of waveguide multiplexing. This scheme employs multiport photodetectors (PDs) to sum the intensities of multiple optical signals, eliminating the need for multiple wavelengths or modes. A 16-port Ge PD with a 3 dB bandwidth of 11.8 GHz at a bias voltage of -3 V is demonstrated, and it can be further scaled up to handle 250 ports while maintaining a 6.1 GHz operation bandwidth. A 4×4 circuit fabricated on a Si-on-insulator (SOI) platform is used to perform MVMs in a 3-layer neural network designed for classifying Iris flowers, achieving a classification accuracy of 93.3%. Furthermore, the performance of large-scale circuits in a convolutional neural network (CNN) for Fashion-MNIST is simulated, resulting in a classification accuracy of 90.53%. This work provides a simplified and scalable approach to photonic MVM, laying a foundation for large-scale and multi-dimensional photonic matrix-matrix multiplication in optical neural networks.
Cited by 0Open access
Ryusuke Egawa, Masayuki Sato, Jubee Tada et al. · 2013
To overcome the memory and power wall problems on a high performance microprocessor for supercomputer systems, the reduction in memory access latencies and its power consumptions is urgently required. Recently, a 2.5D integration technology, which can integrate multiple chips on a silicon die by using vertical interconnects, are expected as key technologies to overcome these problems. Under this situation, this paper explores the design space of a processor and memory module for vector supercomputers using a vertical integration technology. In this study, both a processor and a memory of vector supercomputers are integrated in one silicon die as a single module, and its performance and power are evaluated by leading scientific applications. The evaluation results demonstrated that the 2.5D integration reduces the energy consumption by 83% compared to the conventional PCB implementation.
Cited by 3
Junho Cho, Hoseok Chang, Wonyong Sung · 2006
A SIMD processor that contains a 16-way partitioned data-path is designed for efficient multimedia data processing. In order to automatically align data needed for SIMD processing, the architecture adopts a vector memory unit that consists of 17-bank memory blocks. The vector memory unit also has address generation and rearrangement units for eliminating bank conflicts. The MicroBlaze FPGA based RISC processor is used for program control and scalar data processing. The architecture has been implemented on a Xilinx FPGA, and the implementation performance for several multimedia kernels is obtained.
Cited by 29
Gitam University · Zenodo (CERN European Organization for Nuclear Research) · 2025
<p><em><span>This document demonstrates the process of building a sector-independent Space Vector Modulation (SVPWM) system using a DSP processor in fundamental motor drive systems. The implementation of traditional space vector modulation proves complex because it includes extensive calculations. Before moving forward it is essential to determine the magnitude of voltage vectors according to speed specifications and Volts/Hz data in software and hardware domains. Computing the phase angle and quadrant and sector determination enables the calculation of switching time segments based on decomposition matrices. </span></em></p> <p><em><span>This proposed algorithm dissipates all computational requirements that exist in traditional approaches. The closed loop control system achieves precise switching period control through fixed compare register values which it implements using the Volts/Hz principle. Through its built-in Space Vector Pulse Width Modulation hardware module the TI TMS320LF2407A generates PWM pulses that include four switching states within one PWM period. The performance evaluation of the 4-hp induction motor supplied by IGBT-based inverter modules generated through DSP processor control pulses showed promising results.</span></em></p>
Cited by 0Open access
Arpith C. Jacob, On Harris, Young H. Cho · 2008
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Ingrid Y. Bucher, Margaret L. Simmons · 1991
Delays caused by memory access conjiicts were measured for vector operations on the CRAY Y-MP and CRAY X-MP, and on two versions of the CRAY-2 with static and dynamic memory. The delays were measured as jimctions of vector length and the number of active processors. The observed delays were lowest for memory access operations with stride one. Considerably higher delays were observed for mixed strides or random access. For access operations with mixed strides, measurements indicate that memory access was slowed down by a factor of up to 1.7 for the 8-processor CRAY Y-MP. For the 4processor machines, the factors were 3.1 for the CRAY X-MP, 4.4 for the CRAY-2 with dynamic memory, and 2.5 for the CRAY-2 with static memory. The results are compared with a queueing model of memory bank conjiicts.
Cited by 15Open access
Yang C(杨晨), Cui GX (崔国新), Huang YY (黄寓洋) et al. · 2010
An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.
Cited by 0
Naughton, Thomas J. · Maynooth University ePrints and eTheses Archive (Maynooth University) · 2000
We characterize the bounds on numerical accuracy that a nite acoustic beam height will have on an analog acousto-optic algebra processor that uses coherent illumination. A Fourier optical model of our physical matrixvector multiplier is used as a basis for the simulations.
Cited by 0
K. Aono, M. Toyokura, Toshiyuki Araki et al. · IEEE Journal of Solid-State Circuits · 1992
A 2-GOPS, 60-MIPS DSP with a new vector-pipeline architecture (VDSP: vector digital signal processor) has been developed for video CODEC systems, using 0.8- mu m CMOS technology. The VDSP is programmable and can be adapted to handle various standards for video coding, such as those of CCITT H.261, MPEG (Moving Picture Experts Group), and JPEG (Joint Photographic Experts Group). It also contains a discrete cosine transform (DCT) core as one of the special processing units used to enhance performance. The 12.38-mm*12.90-mm VDSP, which consists of approximately 930 K transistors, operates at a maximum clock rate of 60 MHz. The encoder and the decoder specified in CCITT H.261 (full-CIF mode at 15 frames/s or more, 64 kb/s) can be realized with only two VDSP chips and only one VDSP chip, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 49
Mohammad Attari, Lucas Ferreira, Liang Liu et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2022
This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22 nm FD-SOI technology running at a clock frequency of 800 MHz. The system achieves a maximum detection throughput of 0.75 Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128\times 8$ </tex-math></inline-formula> massive MIMO system.
Cited by 14
Silvia M. Mueller, Christian Jacobi, Hwa-joon Oh et al. · 2012
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low latency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graphics. The FPU has 3 different latencies, optimizing the performance critical single precision FMA operations, which are executed with a 6-cycle latency at an 11FO4 cycle time. The latency includes the global forwarding of the result. These challenging performance, power, and area goals were achieved through the co-design of architecture and implementation with optimizations at all levels of the design. This paper focuses on the logical and algorithmic aspects of the FPU we developed, to achieve these goals. 1
Cited by 0
Martin E. Tanenhaus, Moti Barkan, A. Genusov · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1990
Results are presented of the feasibility study for the GaAs DSP implementation and are compared with previously reported designs. This processor will be incorporated into an insertion module and demonstrates that GaAs DSP replacement modules, reduced to multichip package size, can achieve critical signal processing functions in a typical RF seeker system. Architectural features are offered that effectively make it a high-speed MIMD processor with more than a ten-fold performance advantage over its silicon counterpart. This radar system design provides the compatibility to realize hundreds of megahertz of effective signal bandwidth and precision of performance required.
Cited by 0
Berkel, van, CH Kees, Meuwissen, PPE Patrick, Engin, N · TU/e Research Portal · 2013
A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
Cited by 0
Berkel, CH Kees van, Meuwissen, PPE Patrick, Engin, N · TU/e Research Portal (Eindhoven University of Technology) · 2013
A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
Cited by 0