PARALLEL SORTING ALGORITHMS ON GRID STRUCTURES
TAY SENG CHUAN · National University of Singapore · 1994
Master's
Cited by 0
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About 3,727 papers for “parallel sorting”
TAY SENG CHUAN · National University of Singapore · 1994
Master's
Cited by 0
Tero Harju, Lucian Ilie · 2007
We give a new combinatorial proof, based on stack graphs, for the characterization by forbidden subsequences of the permutations which are sortable on two parallel stacks. Some remarks about the permutations sortable on parallel queues are also made.
Cited by 0
Michael T. Goodrich, Michael Nelson, Nodari Sitchinava · 2007
In this paper, we introduce a model for multicore architectures, which takes into explicit consideration the cache-oriented nature of inputs and outputs in modern CPUs. In addition, we study the fundamental problem of sorting comparable items using this model. We provide algorithms that are efficient in terms of the number of parallel I/O’s. We also provide lower bounds that show that our algorithms are within a constant factor of optimal, for reasonable values of parameters characterizing the number of processors, the size of each processors memory, the size of cache blocks, and the number of items to be sorted.
Cited by 0
E. Schikuta · 2007
Sorting is one of the most important operations in database systems and its efficiency can influences drastically the overall system performance. To speed up the performance of database system, parallelism is applied to the execution of the data administration operations. Conventional parallel hardware architectures, which employ a highly parallel software architecture are used in current parallel database systems. Thereby a common technique is to decluster the data sets among a number of parallel and independent disk drives. In this paper we revisit parallel sorting algorithms in the context of declustered data of parallel database systems. We adapt the well known and well studied parallel sort-merge and bitonic-sort algorithms for declustered data and compare analytically their performance. We show that the adapted bitonic sort outperforms the adapted sort-merge algorithm for declustered data in resemblance to the results of their conventional counterparts. Keyword Parallel Database...
Cited by 0
Kofi Chaim Appiah (14100999) · Figshare · 2009
As the "gigaherts war" comes to an end, the computer industry has turned to increasing the number of processors instead of their speeds as a way to increase performance. A quick look at the progress of this movement reveals a tendency for CPU design to mimic modern GPU design and vice versa. This progression from single to multiple processors requires new ideas and methods to utilize systems efficiently. With this in mind, we investigate a problem common to most programs, sorting and use its example to try to understand the difficulties of adapting to parallel systems. We also examine the disigns of highly parallel systems like modern GPUs and future CPU and GPU hybrids like Sony's Cell and Intel's Larrabee.
Cited by 0Open access
Xue Shirley Li, F. Lockwood Morris · 1992
A miniswap Si,1 ≤ i < n, compares two adjacent keys Пi, Пi+1 in the sequence (П1, ... , Пn), and transposes them if they are out of order. A full sweep is any composition of all n - 1 possible miniswaps. We prove that the composition of any n- 1 full sweeps is a sorting function.
Cited by 0Open access
Cécile Germain, Damien Gautier de Lahaut · Lecture notes in computer science · 1997
Cited by 1
Wei Wang · Journal of Bioresource Management · 2011
With the limitations given by the power consumption (power wall), memory wall and the instruction level parallelism, the computing industry has turned its direction to multi-core architectures. Nowadays, the multi-core and many-core architectures are becoming the trend of the processor design. But how to exploit these architectures is the primary challenge for the research community. To take advantage of the multi-core architectures, the software design has undergone fundamental changes. Sorting is a fundamental, important problem in computer science. It is utilized in many applications such as databases and search engines. In this thesis, we will investigate and auto-tune two parallel sorting algorithms, i.e., radix sort and sample sort on two parallel architectures, the many-core nVIDIA CUDA enabled graphics processors, and the multi-core Cell Broadband Engine. We redesign and manually tune these two parallel sorting algorithms to take advantage of multiple-level parallelism simultaneously, i.e., thread level parallelism, loop level parallelism, data level parallelism (SIMD instructions). At the same time, we try to take advantage of the high-speed shared memory. The experimental results showed that the parallel implementation of these two sorting algorithms on these two multi-core architectures achieved significant performance improvement compared to the corresponding sequential version.
Cited by 0Open access
Stavros D. Nikolopoulos, Stylianos D. Danielopoulos · Microprocessing and Microprogramming · 1994
Cited by 1
S.K. Karmarkar · 2003
A parallel processing system is being developed. Unlike conventional parallel architectures, the parallelism is at the level of an algorithm. A sorting algorithm for this machine is presented. The architecture of the parallel messing system consists of an elevated single instruction multiple data (SIMD) model that works at the level of a basic algorithm. Viewed from another angle, the architecture of the multiple instruction multiple data (MIMD) type, since synchronization is not at the instruction level. In reality, it is midway between SIMD and MIMD, which the author calls an SAMD (same algorithm multiple data) architecture. The philosophy is to divide the problem into a number of algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0
Mark H. Nodine, Jeffrey Scott Vitter · 2001
We present a practical deterministic load balancing strategy for distribution sort that is applicable to parallel disks and parallel memory hierarchies with both single and parallel processors. The simplest application of the strategy is an optimal deterministic algorithm called Balance Sort for external sorting on multiple disks with a single CPU, as described in the companion paper. However, the internal processing of Balance Sort does not seem parallelizable. In this paper, we develop an elegant variation that achieves full parallel speedup. The algorithms so derived are optimal for all parallel memory hierarchies with any type of a PRAM base-level interconnection and are either optimal or best-known for a hypercube interconnection. We show how to achieve optimal internal processing time as well as optimal number of I/Os in parallel two-level memories.
Cited by 0
Thompson, C. D., Kung, H. T. · KiltHub Repository · 2018
Computer Science Department
Cited by 0Open access
With An Experimental, David R. Helman, David A. Bader · 1996
) David R. Helman David A. Bader Joseph J&apos;aJ&apos;a y Institute for Advanced Computer Studies and Department of Electrical Engineering, University of Maryland, College Park, MD 20742 fhelman, dbader, josephg@umiacs.umd.edu Abstract A fundamental challenge for parallel computing is to obtain high-level, architecture independent, algorithms which execute efficiently on general-purpose parallel machines. With the emergence of message passing standards such as MPI, it has become easier to design efficient and portable parallel algorithms by making use of these communication primitives. While existing primitives allow an assortment of collective communication routines, they do not handle an important communication event when most or all processors have nonuniformly sized personalized messages to exchange with each other. We first present an algorithm for the h-relation personalized communicationwhose efficient implementation will allow high performance implementations of a large class ...
Cited by 0
Yuchen He, Behrooz Parhami · 2025
Parallel counters form a well-studied class of arithmetic circuits with numerous implementations, where conventional designs face irregular wiring and long carry chains, especially for a large number of inputs. We focus on sorting-network-based parallel counters that replace cascaded full-adders with sorting stages and minimal logic. Such sorting networks introduce a regular, highly pipelinable structure, eliminating the irregular wiring and long carry chains of conventional full-adder-based counters. We evaluate our design in terms of delay, hardware cost, and delay-cost product, comparing it against conventional architectures. Experimental results show competitive latency for moderate numbers of inputs (7-bit: 10.43 ns vs. 10.57 ns for FA based). For larger counters (15-bit), by properly tailoring the sorting network, the latency outperforms the conventional one (13.56 ns vs 14.85 ns) with significantly higher logic gates cost. The results cited are for FPGA realizations. We anticipate greater benefits with custom VLSI due to the VLSI-friendliness of our design.
Cited by 1
Nicolas Melot, Christoph Keßler, Kenan Avdic et al. · Procedia Computer Science · 2012
The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. It comprises 48 Intel-x86 cores linked by an on-chip high performance mesh network, as well as four DDR3 memory controllers to access an off-chip main memory. We investigate the adaptation of sorting onto SCC as an algorithm engineering problem. We argue that a combination of pipelined mergesort and sample sort will fit best to SCC's architecture. We also provide a mapping based on integer linear programming to address load balancing and latency considerations. We describe a prototype implementation of our proposal together with preliminary runtime measurements, that indicate the usefulness of this approach. As mergesort can be considered as a representative of the class of streaming applications, the techniques developed here should also apply to the other problems in this class, such as many applications for parallel embedded systems, i.e. MPSoC.
Cited by 4Open access
Thompson, C. D., Kung, H. T. · KiltHub Repository · 2018
Computer Science Department
Cited by 0Open access
Torben Hagerup, Hong Shen · Information Processing Letters · 1990
Cited by 22
Roland Häggkvist, Pavol Hell · SIAM Journal on Computing · 1981
We prove that there exist graphs with n vertices and at most $2n^{5/3} \log n$ edges for which every acyclic orientation has in its transitive closure at least $\begin{pmatrix} n \\ 2 \end{pmatrix} - 10n^{5/3} $ arcs. We conclude that with $2n^{5/3} \log n$ parallel processors n items may be sorted with all comparisons arranged in two time intervals. We also show that $\frac{1}{9}n^{3/2} $ processors are not sufficient to achieve the same end. These results are extended to parallel sorting in k time intervals, and related to other work on parallel sorting. The existence of sorting algorithms achieving the bounds is proved by nonconstructive methods. (The constants quoted in the abstract are somewhat improved in the paper.)
Cited by 44
Sanguthevar Rajasekaran · Massive computing · 2002
Cited by 1
Ka Wong Chong, Yijie Han, Yoshihide Igarashi et al. · Lecture notes in computer science · 1999
Cited by 1