K.J. Blow, A. Poustie, R.J. Manning · Nonlinear Guided Waves and Their Applications · 1998
In the early days of computing (1940’s and 1950’s), computers were designed to operate serially as no static memory was available and storage could only be implemented using recirculating delay lines. Modem silicon based computers process data in parallel using static memory and latching logic gates. If processing is to be possible in all-optical form we believe it is necessary to return to serial techniques since it has proved difficult to keep light still and obtain latching. Recent work at Colorado [1] has used these serial techniques to implement a stored program optoelectronic computer using a combination of electronic detection to control lithium niobate gates and optical fibres to provide the optical pathways. The key feature of the bit serial design is to use the time of flight of the light to provide a natural memory and to arrange for computation to occur by appropriate synchronisation of data and control pulses. One advantage of this approach is that the optical processing is scaleable in bit rate. In this paper we will describe an all-optical implementation of these techniques, based on the Nonlinear Optical Loop Mirror (NOLM)[2] switch architecture, with application to the operation of packet switched networks.
Cited by 1
Mike Davies · 2011
Presents a collection of slides covering the following topics: frame processing pipeline; system design; processing capability; Fulcrum Ethernet switch chip.
Cited by 1
Matteo Varvello, Rafael Laufer, Feixiong Zhang et al. · 2014
The rapid growth of server virtualization has ignited a wide adoption of software-based virtual switches, with significant interest in speeding up their performance. In a similar trend, software-defined networking (SDN), with its strong reliance on rule-based flow classification, has also created renewed interest in multi-dimensional packet classification. However, despite these recent advances, the performance of current software-based packet classifiers is still limited, mostly by the low parallelism of general-purpose CPUs. In this paper, we explore how to accelerate packet classification using the high parallelism and latency-hiding capabilities of graphic processing units (GPUs). We implement GPU-accelerated versions for both linear and tuple search, currently deployed in virtual switches, and also introduce a novel algorithm called Bloom search. These algorithms are integrated with high-speed packet I/O to build GSwitch, a GPU-accelerated software switch. Our experimental evaluation shows that GSwitch is at least 7x faster than an equally-priced CPU classifier and is able to reach 10 Gbps with minimum-sized packets and a rule set containing 128K OpenFlow entries with 512 different wildcard patterns.
Cited by 29
nasa · 2018
Future satellite communications applications will require a packet-switched onboard satellite processing system to route packets at very high speeds from uplink beams to different downlink beams. The rapid emergence of point-to-multipoint services, and the important role of satellites in a national and global information infrastructure, makes the multicast function essential to a fast packet switch (FPS). NASA Lewis Research Center's Digital System Technology Branch has been studying possible architectures for high-speed onboard-processing satellite systems. As part of this research, COMSAT Laboratories developed a broadband integrated services digital network (B-ISDN) fast packet switch for Lewis that was delivered on December 1994. The fast packet switch consists of eight inputs and eight outputs that can receive and transmit data, respectively, at a rate of 155 Mbps. The switch features multiple priorities (three) and multiple-size (three) satellite virtual cells that are similar to ATM cells in length (52 bytes). In addition, the fast packet switch features a congestion-control algorithm that allows users to set different thresholds for individual destination ports, thus throttling back the traffic from the transmitting port.
Cited by 0
Zhen Liu, Kai Zheng, Bin Liu · 2006
The exposed memory hierarchies employed in many network processors (NPs) are expensive and hard to be effectively utilized. On the other hand, conventional cache cannot be directly incorporated into NP either because of its low efficiency in locality exploitation for network applications. In this paper, a novel memory hierarchy component, called split control cache, is presented. The proposed scheme employs two independent low latency memory stores to temporarily hold the flow-based and application-relevant information, exploiting the different locality behaviors exhibited by these two types of data. Data movement is manipulated by specially designed hardware to relieve the programmers from details of memory management. Performance evaluation shows that this component can achieve a hit rate of over 90% with only 16 KB of memories in route lookup under link rate of OC-3c and provide enough flexibility for the implementation of most network applications.
Cited by 3
You, C., Zhao, Y., Feng, G. et al. · arXiv (Cornell University) · 2022
Various middleboxes are ubiquitously deployed in networks to perform packet processing functions, such as firewalling, proxy, scheduling, etc., for the flows passing through them. With the explosion of network traffic and the demand for multiple types of network resources, it has never been more challenging for a middlebox to provide Quality-of-Service (QoS) guarantees to grouped flows. Unfortunately, all currently existing fair queueing algorithms fail in supporting hierarchical scheduling, which is necessary to provide QoS guarantee to the grouped flows of multiple service classes. In this paper, we present two new multi-resource fair queueing algorithms to support hierarchical scheduling, collapsed Hierarchical Dominant Resource Fair Queueing (collapsed H-DRFQ) and dove-tailing H-DRFQ. Particularly, collapsed H-DRFQ transforms the hierarchy of grouped flows into a flat structure for flat scheduling while dove-tailing H-DRFQ iteratively performs flat scheduling to sibling nodes on the original hierarchy. Through rigorous theoretical analysis, we find that both algorithms can provide hierarchical share guarantees to individual flows, while the upper bound of packet delay in dove-tailing H-DRFQ is smaller than that of collapsed H-DRFQ. We implement the proposed algorithms on Click modular router and the experimental results verify our analytical results.
Cited by 0Open access
Mihai Dobrescu, Katerina Argyraki, Sylvia Ratnasamy · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2012
Contention for shared resourcesâcaches, memory controllers, buses, NICsâis assumed to be a hurdle in optimizing and predicting the performance of multi-core software systems, especially packet-processing systems, which make extensive use of these resources. Recent projects have demonstrated the feasibility of building such systems with high and predictable performance, but they all make a crucial simplifying assumption: that all processing cores see identical input and run identical code on it, while all packets incur the same kind of conventional packet processing (e.g., IP forwarding). To generalize for realistic scenarios, we must accommodate multiple clients, running a range of both standard and sophisticated packet-processing applications. This introduces the question of how to configure and run a varied mix of packet-processing applications on modern multicore hardware, so as to achieve both ease of programmability and optimal, predictable performance. We set out to answer this question, and we reach a surprising conclusion: in a software-based packet-processing platform, if we follow a few basic programming and configuration rules, (a) contention affects performance in a predictable manner and (b) the effect depends very little on how we schedule different apps on different cores, i.e., contention-aware scheduling is not meaningful; in short, the most efficient way to manage contention is to mostly ignore it.
Cited by 105Open access
Pavel Benáček, Viktor Puš, Jan Kořenek et al. · 2017
The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. The results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.
Cited by 5
Γεώργιος Βασιλειάδης · 2014
Η ανάγκη για διαφορετικού τύπου υπηρεσίες στον πυρήνα του Internet (όπως firewalls, συστήματα ανίχνευσης και πρόληψης επιθέσεων,συστήματα κατηγοριοποίησης της κίνησης του δικτύου, κλπ.), συνεχώς αυξάνει. Οι υπηρεσίες αυτές πρέπει να εκτελούν περίπλοκεςεπεξεργασίες στα πακέτα δεδομένων σε όλα τα επίπεδα της στοίβας δικτύου, οι οποίες, όμως, δεν υποστηρίζονται από τους παραδοσιακούςδρομολογητές. Για το λόγο αυτό, έχουν αναπτυχθεί εξειδικευμένες συσκευές (οι οποίες ονομάζονται "middleboxes").Οι συσκευές αυτές εκτελούν διάφορες μορφές επεξεργασίας - οι οποίες περιλαμβάνουν, για παράδειγμα, τη λεπτομερειακή ανάλυσητων πακέτων, τη κρυπτογράφηση τους και τη συμπίεση. Επιπλέον, η επεξεργασία των πακέτων που βασίζεται αποκλειστικά σελογισμικό υπόσχεται την ταχεία ανάπτυξη νέων, εξελιγμένων μορφών επεξεργασίας, χωρίς την ανάγκη για αγορά ακριβού εξοπλισμού.Σε αυτή την διατριβή, προτείνουμε τη χρήση μονάδων επεξεργασίας γραφικών (GPUs) προκειμένου να αυξήσουμε την απόδοση τωνεφαρμογών επεξεργασίας πακέτων δικτύου. Οι GPUs έχουν εξελιχθεί σε υπολογιστικές συσκευές οι οποίες προσφέρουν μαζικόπαραλληλισμό, καθώς περιέχουν εκατοντάδες πυρήνες επεξεργασίας που μπορούν να χρησιμοποιηθούν για υπολογισμούς γενικής χρήσης,πέρα από την χρήση τους σε εφαρμογές γραφικών. Ωστόσο, λόγω των διαφορετικών ιδιοτήτων και περιορισμών των GPUs, δεν είναιπάντα εύκολη υπόθεση να βελτιωθεί η απόδοση του υπάρχοντος λογισμικού.Η παρούσα διατριβή αναλύει τη χρήση GPUs για την επεξεργασία πακέτων δικτύου (με εποπτεία κατάστασης) και περιγράφειτεχνικές που απαιτούνται ώστε να βελτιωθεί η επίδοση της. Αρχικά, παρουσιάζουμε μια μελέτη σχετικά με την επιτάχυνση τηςεπεξεργασίας πακέτων χρησιμοποιώντας διακριτές κάρτες γραφικών. Δεύτερον, παρουσιάζουμε μια ευρύτερη αρχιτεκτονικήεπεξεργασίας πακέτων που παραλληλοποιεί προσεκτικά την επεξεργασία και ανάλυση των πακέτων σε τρία επίπεδα,χρησιμοποιώντας (i) διασυνδέσεις δικτύου με πολλαπλές ουρές, (ii) πολλαπλούς επεξεργαστές (CPUs), και (iii) πολλαπλές GPUs.Τέλος, διερευνούμε το σχεδιασμό ενός framework για την επεξεργασία πακέτων βασισμένο σε GPUs, το οποίο προσδιορίζειέναν αρθρωτό (modular) μηχανισμό για τον προγραμματισμό εφαρμογών επεξεργασίας πακέτων, το οποίο περιορίζει τις μεταφορέςδεδομένων και τις περιττές επεξεργασίες. Τα πειραματικά αποτελέσματα μας δείχνουν ότι η ορθή υλοποίηση εφαρμογών επεξεργασίαςπακέτων βασισμένες σε GPUs, μπορεί να βελτιώσει σημαντικά την απόδοση σε σύγκριση με μία πολυ-πύρινη CPU.
Cited by 0Open access
Yasusi Kanada · 2014
A network processor (NP) usually contains multiple packet processing cores (PPCs) and a control processing core (CPC), and the synchronization and communication between CPC and PPCs, which is required for controlling an NP, is very complex. To reduce the complexity, a method for controlling packet processing in NPs by using PPCs is proposed. By means of this method, complex control messages are partially processed and divided into simplified control packets by a CPU outside the NP chip, and these packets are sent to a control-processing PPC. The control-processing PPC controls data-processing PPCs by using data-exchange mechanisms, such as a shared memory or an on-chip network, which are more uniform and simpler than those between a CPC and PPCs. This control method is applied to a virtual-link control-processing task and packet-processing tasks in a network node with a virtualization function. Both tasks are described by a hardware-independent high-level language called "Phonepl," and communication between the PPCs is programmed following normal and uniform shared-memory semantics. As a result, programming the control-processing task and porting the program become much easier.
Cited by 5
H. Avramopoulos · 2004
We discuss the use of SOA-based interferometric gates for optical packet switching applications. Based on these modules, key signal processing functionalities required by a packet switched node are demonstrated directly in the optical domain.
Cited by 0
Leif Johansson, Per Holmberg, Robert Skog · Ericsson Technology Review · 2022
There are several ways to improve the energy efficiency of mobile communication systems and reduce the amount of energy it takes to provide mobile broadband services.
Cited by 1Open access
Yong Liu · SPIE Newsroom · 2007
Cited by 1
Martin Košek, Jan Kořenek · 2007
Network security systems become an essential part of many network structures in both company and university domains. These systems however require a higher semantic level of network traffic analysis like stateful filtration or TCP stream reassembling. This paper deals with an architecture of flexible FlowContext platform capable of stateful processing at multigigabit speeds. It allows to analyze and process incoming network traffic with a flow-based approach rather than packet-based one. The proposed architecture is flexible in supporting wide range of applications, allows performance scalability and state information consistency checking. The advantages and flexibility of proposed platform is demonstrated on several network security applications.
Cited by 4
Viktor Puš, Jiří Tobola, Vlastimil Košař et al. · 2011
Many algorithms and hardware architectures are proposed to increase processing speed of time-critical operations in the field of longest prefix matching, packet classification and regular expression matching. Despite this fact, there is still no free and easily extensible platform for evaluation, comparison and experiments with existing approaches. We propose the Net bench Framework which aims to serve as an independent platform for researchers seeking the easiest way to implement their algorithms, as well as the comparison of their algorithms with reference implementations of other approaches. The framework is provided as an open source and can be easily extended to support new algorithms or new comparison methodology. Net bench is publicly available at http://www.fit.vutbr.cz/netbench.
Cited by 16
LI Ru-wei, BAO Chang-chun · SHILAP Revista de lepidopterología · 2007
The main reasons of packet loss were described and the related techniques of packet loss were introduced.Packet loss processing techniques,which include packet loss concealment and packet loss recovery,were used to recover and conceal the packet loss.And the aim of packet loss prevention was to prevent network congestion in order to reduce the packet loss rate.In addition,the current situation and trend about VoIP were given and discussed.
Cited by 0Open access
S. J. Ben Yoo · 2014
Abstract: This paper discusses important signal processing functions in all-optical packet routing systems. We will pay special attention to all-optical time-to-live, optical performance monitoring, optical label swapping, and optical regeneration. The new optical packet switching router is capable of all-optically achieving necessary routing functions including signal processing typically handled by optoelectronics.
Cited by 0
István Finta, Gergely Elias, Janos Illes · 2018
In the course of transmission through networks a particular packet, like a Storm tuple or a performance/fault management (PM/FM) report in XML format of an Operation Support SystemOSS) application, data loss/out of order arrival/duplication phenomena may cause the packet not to arrive at the destination, to arrive exactly once or to arrive in several copies. Vast literature explores typical distributions for packet loss/duplication. At each layer of the network the entities processing the packets need to cope with packet loss/duplication in a certain way. In some cases loss/duplication does not matter too much. In other cases losses/duplications need to be very strictly handled. At the application level such strict handling is a must in case of an OSS application: missing or duplicated PM data may cause a wrong perception about the real performance of the network. In such cases for every received packet the receiving end needs to check whether the packet has already been received or not and then to insert it exactly once. The efficiency of the checking depends on the data structure being used for storing the packets or their keys. In this contribution we construct a model about typical statistical distribution of packet loss and duplication in stream processing environment. Then through the parameters of the model we assess the performance of an interval-based, lightweight, high speed filtering tree against traditional binary search trees.
Cited by 2
J. W. Schumacher · 2015
Experiments in high-energy physics (HEP) and related fields often impose constraints and challenges on data acquisition systems. As a result, these systems are implemented as unique mixtures of custom and commercial-off-the-shelf electronics (COTS), involving and connecting radiation-hard devices, large high-performance networks, and computing farms. FELIX, the Frontend Link Exchange, is a new PC-based general purpose data routing device for the data-acquisition system of the ATLAS experiment at CERN. Performance is a very crucial point for devices like FELIX, which have to be capable of processing tens of gigabyte of data per second. Thus it is important to understand the performance limitations for typical workloads on modern hardware. In this paper the analysis of FELIX packet processing algorithm is presented. The role played by the PC system's memory architecture in the overall data throughput is discussed and motivated, both by measurements and theoretical means. Finally, optimizations increasing the processing throughput by a factor larger than 10x are analyzed.
Cited by 6Open access
Tsai Chi Huang, Cecil O. Alford, Frederick W. B. Li · UPT. Syiah Kuala University Library (Syiah Kuala University) · 2001
The bandwidth of communication channels has increased dramatically in recent years due to the introduction of fiber-optic links. Organizing and processing the data that is being transferred over these high performance communication networks has become a major obstacle. This research addresses the issue of UDP/TCP/IP processing overhead in an Instruction Set Architecture (ISA). The research will define the processing overhead and develop architectural enhancements to improve performance. The research contributions are divided as follow: (1) Developed a UDP/TCP/IP packet handling program that can be executed by a single CPU as a protocol processing benchmark. The program performance and functionality was validated using a commercial UDP/TCP/IP program. (2) Developed and implemented a superscalar processor simulator JAESS that can execute the UDP/TCP/IP protocol stack program from the previous task as an evaluation platform. In addition, an analytical method to validate superscalar processor performance was developed. (3) Characterize UDP/TCP/IP packet processing overhead where the simulated results showed excessive memory instruction execution while the overall instruction execution pattern varied insignificantly for different protocols, UDP/IP or TCP/IP, and packet sizes, 512 or 1024 byte packets. (4) Developed and evaluated the Precise Out-of-order Memory Execution (POME) method to improve memory instruction processing.
Cited by 0Open access