C.H. Berkel, van, P.P.E. Meuwissen, N. Engin · Data Archiving and Networked Services (DANS) · 2013
A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
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Nikolay Dikarev, Aleksandr Shmelëv · ITNOU Information technologies in education science and management · 2021
The article is devoted to the analysis of the Quicksort execution in the vector dataflow proces-sor that uses the vector-pointer method for storing arrays.
Cited by 1
Alireza Bakhshai, G. Joós, José Espinoza et al. · 2002
This paper presents a novel approach to the implementation of the space vector modulation (SVM). The proposed technique takes advantage of a modified Kohonen's competitive layer to calculate the on duration of the adjacent switching state vectors. By using this technique: (a) the hardware and software complexity of the system is reduced; (b) the maximum attainable switching frequency and thus the bandwidth of the control system is increased; and (c) the waveform degradation and parasitic harmonics resulting from inaccurate calculations are avoided. The proposed method is compared to the conventional implementations of SVM techniques in terms of hardware/software requirements, switching frequency, computation time, and harmonic spectra. The method is applied to a DSP controlled 3 kVA unit (voltage source inverter) and experimental results verify the validity of theoretical and simulation results.
Cited by 17
Patrick Schmidt, Johannes Pfau, Tim Hotfilter et al. · 2024
In recent years, Deep Neural Networks (DNNs) have become common in the embedded domain for a wide variety of tasks. However, due to strict area and energy requirements, dedicated accelerators for these networks are necessary. Different architectures to fulfill this role are available, but an accelerator targeting the ultra-low area design point is still missing. In this work, we present an architecture focusing on minimizing resource utilization and energy requirements. We propose a small-scale vector processor that can be integrated into a RISC-V core. Unlike traditional, feature-rich vector instruction sets, we instead determine the most crucial instructions for DNN workloads through hardware-software co-design. To evaluate our implementation, we integrate our vector extension into an open-source RISC-V System-on-Chip, the NeoRV32, and measure the hardware overhead and achieved acceleration of operations commonly found in neural networks. Our results show an acceleration of up to 11.9x on convolutional workloads over the baseline architecture, while we demonstrate that our implementation introduces significantly less hardware overhead than previous works. We provide our work open-source to use for further exploration of low area design of VPUs<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>.<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>https://github.com/itiv-kit/rvve
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Di Giampietro, Aurora · AMS Degree Thesis (University of Bologna) · 2024
Questo studio si focalizza sull’ottimizzazione del processore vettoriale Spatz basato su RISC-V, tramite l’integrazione dell’acceleratore tensoriale RedMulE, progettato per formati low-precision floating-point (FP16). Sono state esaminate due modalità di integrazione di RedMulE: come acceleratore hardware collegato alla TCDM dello Spatz cluster (L1-coupled), e collegato al VRF del core vettoriale (VRF-coupled), integrato quindi all’interno di Spatz stesso. La seconda soluzione consente una cooperazione più stretta tra il processore vettoriale e l’acceleratore ed è stata adottata per il tapeout del chip Maestro. La versione VRF-coupled di RedMulE ha portato a vantaggi in termini di area e prestazioni, senza compromettere le performance del sistema. A livello microarchitetturale, la riduzione del buffer X ha comportato una diminuzione del 6% dell’area occupata da RedMulE. A livello macroarchitetturale, la rimozione delle porte verso la TCDM di RedMulE ha semplificato l’intera interconnect, portando ad una riduzione di circa 170 kGE nell’area complessiva del cluster. Sul fronte delle prestazioni, il collegamento di RedMulE con il VRF ha consentito un miglior sfruttamento della località dei dati, poiché Spatz e RedMulE condividono il VRF e possono comunicare direttamente, evitando di passare attraverso la TCDM. Ciò ha eliminato un livello di movimento dei dati, riducendo le inefficienze temporali ed energetiche. RedMulE, essendo un’architettura specializzata unicamente in calcolo matriciale, ha migliorato l’efficienza energetica dello Spatz cluster durante le moltiplicazioni di matrici FP16. La potenza consumata per l’operazione è aumentata di un fattore di circa 2x ma con uno speedup di 3x. Questo speedup è analogo a quello ottenuto con la versione L1-coupled di RedMulE, confermando che RedMulE VRF-coupled ha portato a miglioramenti senza compromettere le prestazioni del sistema.
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Gary K. Felton, John L. Nieber · Transactions of the ASAE · 1992
Finite element programs were executed on scalar machines and a vector processor to evaluate the differences in machines and the effect of writing the code to take the maximum advantage of vector processing. The vector processor ran the original models 17.7 times faster than the scalar machine, and the vectorized code ran 12.0 times faster than the scalar code.
Cited by 1
David Casasent, Steven Riedl · Optics Communications · 1988
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Andréas Karlsson · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2010
The Division of Computer Engineering at Linköping's university is currently researching the possibility to create a highly parallel DSP platform, that can keep up with the computational needs of upcoming standards for various applications, at low cost and low power consumption. The architecture is called ePUMA and it combines a general RISC DSP master processor with eight SIMD co-processors on a single chip. The master processor will act as the main processor for general tasks and execution control, while the co-processors will accelerate computing intensive and parallel DSP kernels.This thesis investigates the performance potential of the co-processors by implementing matrix algebra kernels for QR decomposition, LU decomposition, matrix determinant and matrix inverse, that run on a single co-processor. The kernels will then be evaluated to find possible problems with the co-processors' microarchitecture and suggest solutions to the problems that might exist. The evaluation shows that the performance potential is very good, but a few problems have been identified, that causes significant overhead in the kernels. Pipeline mismatches, that occurs due to different pipeline lengths for different instructions, causes pipeline hazards and the current solution to this, doesn't allow effective use of the pipeline. In some cases, the single port memories will cause bottlenecks, but the thesis suggests that the situation could be greatly improved by using buffered memory write-back. Also, the lack of register forwarding makes kernels with many data dependencies run unnecessarily slow.
Cited by 4Open access
Mohammad Attari, Jesús Rodríguez Sánchez, Liang Liu et al. · 2021
This paper sets out to create an implementation for fingerprint-based positioning using massive multiple-input multiple-output (MIMO) technology, by means of deep convolutional neural networks (CNN), and utilizing the wireless channel state information (CSI). Due to the sheer volume of computational requirements imposed by CNN processing, an accelerator- assisted design is well-suited to the task at hand. Consequently, an application specific instruction set processor (ASIP) is designed to combine flexibility with implementation efficiency. This ASIP is equipped with vector processing capabilities employing a single instruction multiple data (SIMD) scheme, and additionally has a very large instruction word (VLIW) architecture to further exploit instruction-level parallelism. A configurable 2D array of processing engines (PE) is integrated into the processor, in a tightly coupled manner, to accelerate the CNN operation. Synthesis results will be demonstrated using the GF-22 nm FD- SOI technology with a clock frequency of 555 MHz. The system can achieve a throughput of 271 positionings/s, with an average positioning error of 3.5 λ (40 cm) at a carrier frequency of 2.6 GHz.
Cited by 5
Wilfried Oed, Otto Lange · IEEE Transactions on Computers · 1985
Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth. The authors present some analytical results for the calculation of the resulting effect bandwidth for one and two access streams to a memory system in a vector processor. In particular, conditions for conflict-free access are given together with some conflicting cases that should be avoided. Finally, examples of measurements on a Cray X-MP and corresponding simulations are presented.
Cited by 96
P. Sadayappan, Ye Ling, Karl Olson et al. · IEEE Transactions on Robotics and Automation · 1989
The authors propose a restructurable architecture based on a VLSI robotics vector processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is composed of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in each processor, the RVP contains a triple register-file, dual shift network, and dual high-speed input/output (I/O) channels to satisfy the storage and data movement demands of the computations targeted. Efficiently synchronized multiple-RVP configurations, which may be viewed as variable very-long-instruction-word architectures, can be constructed and adapted to match the computational requirements of specific robotics computations. The use of the RVP is illustrated through a detailed example of the Jacobian computation, demonstrating good speedup over conventional microprocessors even with a single RVP. The RVP has been developed to be implementable on a single VLSI chip using 1.2- mu m CMOS technology, so that a single-board multiple-RVP system can be targeted for use on a mobile robot.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 31
Naoya Yamashita, Tadashi Shibata · Japanese Journal of Applied Physics · 2012
A digital processor dedicated to edge-based image vector generation has been developed aiming at real-time image recognition. The processor consists of an on-chip memory and 16 single instruction multiple data (SIMD) processing elements. The capacity of the on-chip memory as well as the overhead for starting the processing have been minimized by introducing a seamless data transferring scheme from memory to processing elements. The 16 SIMD processing elements work together either as accumulators or as shift registers, thus achieving a very efficient generation of two different kinds of feature vector: projected principal-edge distribution (PPED)[3,4] and averaged principal-edge distribution (APED).[5] Concurrent use of these two vectors is shown to be very important for robust image recognition.[5] The chip was fabricated using 0.18-µm complementary metal oxide semiconductor (CMOS) technology and the generation of 64-dimension PPED and APED vectors at 84.7 and 83.9 fps, respectively, from video graphics array (VGA) size images was demonstrated at 62.5 MHz.
Cited by 1
Sq Zhang, Sm Lin, Chen‐Li Cheng · Microwave and Optical Technology Letters · 1993
Abstract An optical fuzzy matrix‐vector processor is designed to implement fuzzy associative memory. By spatial encoding and thresholding operation, the two basic operations needed by fuzzy associative memory, maximization and minimization, are realized optically. Experimental results are given as well. © 1993 John Wiley & Sons, Inc.
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Yiwei Xie, Xiyuan Ke, Shihan Hong et al. · Science Advances · 2025
Matrix-vector multiplication is a fundamental operation in modern signal processing and artificial intelligence. Developing a chip-scale photonic matrix-vector multiplication processor (MVMP) offers the potential for notably enhanced computing speed and energy efficiency beyond microelectronics. Here, we propose and demonstrate a 16-channel programmable on-chip coherent photonic processor capable of performing complex-valued matrix-vector multiplication at a computing speed of 1.28 tera-operations per second (TOPS). Low phase error Mach-Zehnder interferometers mesh and ultralow-loss broadened photonic waveguide delay lines are firstly combined for optical computing, enabling the encoding of amplitude and phase information, along with high-speed coherent detection. The proposed MVMP demonstrates high flexibility in implementing various functions, including arbitrary matrix transformation, parallel image processing, and handwritten digital recognition. Our work demonstrates the MVMP's advantages in scalability and function flexibility, enabled by the low-loss and low phase error designs, making a substantial advancement in high-speed and large-scale photonic computing technologies.
Cited by 17Open access
Christopher Han-Yu Chou · 2010
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Ashraf Mohamed Hemeida, S.A. Hassan, Salem Alkhalaf et al. · Ain Shams Engineering Journal · 2020
This paper is focused on Intel Advanced Vector Extension (AVX) which has been borne of the modern developments in AMD processors and Intel itself. Said prescript processes a chunk of data both individually and altogether. AVX is supporting variety of applications such as image processing. Our goal is to accelerate and optimize square single-precision matrix multiplication from 2080 to 4512, i.e. big size ranges. Our optimization is designed by using AVX instruction sets, OpenMP parallelization, and memory access optimization to overcome bandwidth limitations. This paper is different from other papers by concentrating on several main technique and the results therein. Making parallel implementation guidelines of said algorithms, where the target architecture’s characteristics need to be taken into consideration when said algorithms are applied are presented. This work has a comparative study of using most popular compilers: Intel C++ compiler 17.0 over Microsoft Visual Studio C++ compiler 2015. Additionally, a comparative study between single-core and multicore platforms has been examined. The obtained results of the proposed optimized algorithms are achieved a performance improvement of 71%, 59%, and 56% for C = A.B, C = A.BT, and C = AT.B separately compared with results that are achieved by implementing the latest Intel Math Kernel Library 2017 SGEMV subroutines.
Cited by 10Open access
D. R. Winder, Bruce Loftis · Advances in X-ray Analysis · 1983
The CYBER 205 has a number of features applicable to the manipulation of the powder diffraction file (PDF). The FORTRAN language has been extended to include many vector procedures and calls to internal system procedures (e.g., the system clock, is accessible and timing of routines is accurate to a microsecond). A VECTOR is specified by its address and its length. A pointer to a vector, a DESCRIPTOR, can be assigned and then used in arithmetic and relational expressions. A BIT vector is a binary switch such that a bit value (ON or OFF) can control the disposition of a corresponding element of a vector. The maximum size of a vector is 65535 elements.
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SHAW, HERBERT JOHN, GOODMAN, JOSEPH W., BOWERS, JOHN E. et al. · Institutional Repository of Xi'an Institute of Optics and Fine Mechanics, Chinese Academy of Sciences (Xian Institute of Optics and Precision Mechanics) · 1984
An array (48, 49, 50, 51 ) of fiber optic couplers coupling an input (45) and an output (46) waveguide. The output waveguide (46) is routed among the couplers of the array such that either backward or forward coupling exists. With backward coupling, energy coupled into the output waveguide (46) in a coupler of the array is guided back to the preceding coupler for coupling back into the input waveguide (45). The backward coupling allows recirculations to occur between couplers to create poles and zeroes in the transfer function of the array which transfer function can be programmed or tailored somewhat to have specific characteristics. Further, the backward coupling allows the array to be used for matrix-vector multiplication.
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Danil V. Bogayevskiy, Sergey Ezhov, Dmitrii Kaplun et al. · 2019
In this paper, we propose an implementation approach to the system profiling of the virtual architecture based on the QEMU emulator. This approach is distinguished by the ability to explore guest models of vector processors. Moreover, the recommendations for optimizing vectorization obtained through profiling on the vector processor model are given.
Cited by 6
Berkel, van, C.H., Meuwissen, P.P.E., Engin, N. et al. · TU/e Research Portal · 2003
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