Giulio Antonini, Antonio Orlandi · IEEE Transactions on Electromagnetic Compatibility · 2001
Existing techniques for recognizing and identifying disturbed signals waveforms are primarily based on visual inspection. This paper proposes a wavelet packet based technique to perform a feature extraction from the disturbance signal and a classification of the extracted features in order to identify the possible causes of the disturbance. The same wavelet based procedure is applied to signal compression and denoising in order to make the EMC analysis of the data easier.
Cited by 51
Systems and Means of Informatics · 2017
Cited by 0
Xu Q., Miano S., Gao X. et al. · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 2025
With the slowdown of Moore's law, CPU-oriented packet processing in software will be significantly outpaced by emerging line speeds of network interface cards (NICs). Single-core packet-processing throughput has saturated. We consider the problem of high-speed packet processing with multiple CPU cores. The key challenge is state-memory that multiple packets must read and update. The prevailing method to scale throughput with multiple cores involves state sharding, processing all packets that update the same state, e.g., flow, at the same core. However, given the skewed nature of realistic flow size distributions, this method is untenable, since total throughput is limited by single-core performance. This paper introduces state-compute replication, a principle to scale the throughput of a single stateful flow across multiple cores using replication. Our design leverages a packet history sequencer running on a NIC or top-of-the-rack switch to enable multiple cores to update state without explicit synchronization. Our experiments with realistic data center and wide-area Internet traces show that state-compute replication can scale total packet-processing throughput linearly with cores, independent of flow size distributions, across a range of realistic packet-processing programs.
Cited by 0
Nanda Kishore, Dr. S. Rajarajeswari, Dr. Anita Kanavalli · Zenodo (CERN European Organization for Nuclear Research) · 2021
With the evolution of internet, we see huge spike in number of network users. The range of generated internet traffic in most of the various locations is increasing rapidly. Latest networking environment should deliver high throughput, high speed, high bandwidth and less delay properties to cope up with the new era of internet. The traditional data packet acquisition and distribution operations and packet processing capabilities may fail to agree with the new standards of faster data packet processing, in turn leads to data loss, which is costly in packet processing. This survey contributes on finding a faster packet processing framework to overcome the challenges faced by traditional network packet processing frameworks in networking environments. This paper aims at packet acquisition and distribution method based on Data plane development kit (DPDK) and other traditional packet processing models, which can productively decrease packet loss and successively enhance the performance rate in networking environment. It can also help in reducing resource waste in packet acquisition and distribution. Comparison between the packet processing frameworks show that Data plane development kit-based network data processing has better performance compared to Netmap Netsclice and PF-RING in faster packet processing.
Cited by 0Open access
Nhu-Ngoc Dao (3141558), Joongheon Kim (3141567), Minho Park (3141564) et al. · Figshare · 2016
Cited by 0Open access
Amit Kumar, Mishra Professor, R Bolla et al. · 2023
The process of choosing energy-efficient networking tools and devices while limiting resource use is known as green networking.Which pipeline best captures the performance and behaviour of an energy-aware network gadget with Ability to use LPI plus AR?The major objective is to manage both pipeline power setup and optimal method of traffic flow distribution.Modern packet processing engines, which frequently consist of a variety of concurrent pipelines to "divide and conquer" the amount of incoming traffic, were the subject of this work.This work focuses on energy-aware gadgets that can lower their energy needs by adjusting their performance.In order to do so properly depict the effects of technologies for green networks (such reduced power idle as well as adaptive capacity) on network-and energy-aware performance measures, it suggests an analytical model.The model has been tested by applying real-world traffic traces and energy-conscious software routers, with positive results.In order to dynamically modify the design of energy-aware devices to reduce energy consumption while managing incoming traffic volumes along with achieving network performance requirements, an optimization process predicated upon the framework has been presented also then put to the test in experiments..
Cited by 0Open access
Harjot Gill, Dong Lin, Trisha Kothari et al. · 2012
We present our initial work on SP4 (stands for Scalable Programmable Packet Processing Platform), a software-based programmable packet processing platform that supports (1) stateful packet processing, (2) uses a task-stealing architecture to leverage multi-core processing capabilities in a load-balanced manner, (3) declarative language for rapidly composing and customizing packet processing elements. We have developed a prototype of SP4 by integrating a declarative networking engine with the Intel TBB library and the ACE high-performance communication library. We present the initial results of our SP4 prototype’s capabilities in performing high throughput analysis of SMTP traffic. 1.
Cited by 0
Yunchun Li, Xinxin Qiao · 2011
The demand of network packet processing is increasing as applications demand more and more bandwidth and computing capability. In this paper, the characteristics of packet processing and multi-core systems are analyzed. In order to analyze the differences of serial packet processing and parallel packet processing, the packet processing model is proposed. In the end, a DPI experiment on a multi-core system has been carried out to verify the analysis. The results show the proportion of the parallel part and the load balancing of computing resources affect performance.
Cited by 5
Xian Zhang · International Journal of Performability Engineering · 2018
According to the characteristics of pipeline structure and multi-core processor structure for packet processing in network detection applications, the horizontal-based parallel architecture model and tree-based parallel architecture model are proposed for packet processing of Snort application. The principle of a tree-based parallel architecture model is to use pipelining and flow-pinning technology to design a processor that is specifically used to capture data packets, and other processors are responsible for other stages of parallel processing of the data packets. The experimental comparison and analysis show that the tree-based parallel architecture model has higher performance on the second-level cache hit ratio, throughput, CPU utilization, and inter-core load balancing compared to the horizontalbased parallel architecture model for packet processing of Snort application.
Cited by 0Open access
Atte Virtanen · Aaltodoc (Aalto University) · 2013
Cited by 0
Hayato Yamaki, Hiroaki Nishi · 2016
It will become a serious problem to increase power consumption of routers resulting from explosive increase of network traffics caused by IoT data, big data, and so on. Table lookups in packet processing are known as a bottleneck of the router from the points of both processing performance and power consumption. Packet Processing Cache (PPC), which accelerates the table lookups and reduces the power consumption of them by using cache mechanism, was proposed. However, it is difficult for PPC to obtain high cache hit rate because the size of PPC should be small, such as a L1 cache of processors, to get higher access speed. For this reason, an effective line replacement algorithm was considered in this study for reducing a cache miss without increasing the cache size. First, defects of applying typical line replacement algorithms to PPC were examined. Secondly, two algorithms, LRU Insertion Policy (LIP) and Elevator Cache (ELC), and improved algorithms of LIP and ELC called LIP1, LIP2, ELC1, and ELC2 were considered for improving the above defects. In simulation, it was shown Elevator Cache could reduce the cache miss by at most 17.4% compared with Least Recently Used, which applied to many cache systems.
Cited by 9
Nedeljko Vasić, Marco Canini, Dejan Kostić et al. · 2013
With the abstraction of a logically centralized, global view of the network, Software-Defined Networking (SDN) is poised to dramatically streamline network management and enable extensibility and customization. However, as in every software system, there is always the risk of software faults (or bugs). OpenFlow, currently the standard SDN platform, is particularly subject to such risk because all popular controller frameworks (e.g., NOX, FloodLight, etc.) offer an API that closely matches the low-level OpenFlow interface—so exposing developers to all the idiosyncrasies of the underlying asynchronous and distributed collection of switches [1]. To address several of these issues, Monsanto et al. [2] propose programming language techniques that raise the abstractions for managing SDNs and Reitblatt et al. [3]
Cited by 0
Peter Perešíni, Maciej Kuźniar, Nedeljko Vasić et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2013
In this poster and demo, we showcase a new class of problems that can occur due to inconsistent packet processing at an OpenFlow controller. We proceed to outline a potential solution.
Cited by 0Open access
N. N. Kishore, S. Rajarajeswari, Pramod Sunagar et al. · Lecture notes in electrical engineering · 2022
Cited by 2
Chih-Hsun Chou, Laxmi N. Bhuyan · 2015
As processor power density increases, thermal and power control becomes critical for application processing. In this paper, we consider network applications which feature ON/OFF execution pattern, that causes frequent temperature and power consumption changes in the processor. A novel power aware thermal management algorithm is designed to achieve power saving in multicore processors by employing a vacation scheme. We implement the scheme through the idle states (C-state) provided by the OS in the CPU and show their effectiveness both through analysis and experimental data. Then, we apply our scheme with the thermal constraint and propose a heterogeneous load distribution, which creates more opportunities for power saving. Besides maintaining processor temperature below the temperature constraint, our technique achieves higher sustainable load and better power saving with minimum latency increase compared to existing thermal management techniques. To the best of our knowledge, this is the first work to discuss and develop vacation algorithm considering power, temperature and latency for network application on a general purpose multicore processor.
Cited by 4
Hill, MT Martin, Srivatsa, A, Calabretta, N Nicola et al. · UWA Profiles and Research Repository (University of Western Australia) · 2001
A 1×2 all-optical packet switch is presented. The header processing is implemented by using a SLALOM structure and an optical flip-flop memory is used to store the processed header bits. The packets are switched in wavelength by using cross-gain modulation. Experimental results are presented
Cited by 2
Rui Lu, Zhichuan Guo · Micromachines · 2023
Compared to a stateless data plane, a stateful data plane offloads part of state information and control logic from a controller to a data plane to reduce communication overhead and improve packet processing efficiency. However, existing methods for implementing stateful data planes face challenges, particularly maintaining state consistency during packet processing and improving throughput performance. This paper presents a high-performance, FPGA (Field Programmable Gate Array)-based stateful packet processing approach, which addresses these challenges utilizing the PHV (Packet Header Vector) dynamic scheduling technique to ensure flow state consistency. Our experiments demonstrate that the proposed method could operate at 200 MHz while adding 3-12 microseconds latency. The method we proposed also provides a considerable degree of programmability.
Cited by 1Open access
Hardware Florian Braun, Florian Braun, John Lockwood et al. · 2002
A library of layered protocol wrappers has been developed that process Internet packets in reconfigurable hardware. These wrappers can be used with a reprogrammable network platform called the Field Programmable Port Extender (FPX) to rapidly prototype hardware circuits for processing Internet packets. We present a framework to streamline and simplify the development of networking applications that process ATM cells, AAL5 frames, Internet Protocol (IP) packets and UDP datagrams directly in hardware. 1.
Cited by 0
Gallenmüller, Sebastian · mediaTUM (Technical University of Munich) · 2021
Cited by 0
Y. Liu, E. Tangdiongga, Z. Li et al. · TU/e Research Portal · 2006
We present some progress in the field of optical signal processing that could be utilized in all-optical packet switching. We demonstrate error-free 160 Gb/s optical wavelength conversion employing a single semiconductor optical amplifier. The gain recovery time of the semiconductor optical amplifier is greater than 90 ps. Assisted by an optical bandpass\nfilter, an effective recovery time of 3 ps is achieved in the wavelength converter, which ensures 160 Gb/s operation. This optical wavelength converter can be controlled by a monolithically integrated optical flip-flop memory to route 80 Gb/s data-packets all-optically. The routing is realized without electronic control. The integrated optical flip-flop is\nbased on two-coupled lasers, exhibits single-mode operation, has 35 dB contrast ratio between the states and switches state in about 2 ns. We demonstrate that the integrated flip-flop is able to control the optical wavelength converter up to 160 Gb/s. The system is capable of routing 80 Gb/s data packets with duration of 35 ns, separated by 15 ns of guard time.
Cited by 6