TUR, MOSHE, GOODMAN, JOSEPH W., SHAW, HERBERT J. et al. · Institutional Repository of Xi'an Institute of Optics and Fine Mechanics, Chinese Academy of Sciences (Xian Institute of Optics and Precision Mechanics) · 1986
An array (48, 49, 50, 51) of fiber optic couplers coupling an input (45) and an output (46) waveguide. The output waveguide (46) is routed among the couplers of the array such that either backward or forward coupling exists. With backward coupling, energy coupled into the output waveguide (46) in a coupler of the array is guided back to the preceding coupler for coupling back into the input waveguide (45). The backward coupling allows recirculations to occur between couplers to create poles and zeroes in the transfer function of the array which transfer function can be programmed or tailored somewhat to have specific characteristics. Further, the backward coupling allows the array to be used for matrix-vector multiplication.
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Cano, G., García-Rodríguez, J., Orts, S. et al. · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2017
In this work we discuss the benefits of using computational intelligence methods, like Support Vector Machines (SVM) for the optimization of the prediction of compounds solubility. SVMs are trained with a database of known soluble and insoluble compounds, and this information is being exploited afterwards to improve Virtual Screening (VS) prediction. The landscape in the high performance computing arena opens up great opportunities in the simulation of relevant biological systems and for applications in bioinformatics, computational biology and computational chemistry. Larger databases increase the chances of generating hits or leads, but the computational time needed for the calculations increases not only with the size of the database but also with the accuracy of the VS methods and the model. We discussed the benefits of using massively parallel architectures, in particular graphics processing units. We empirically demonstrate that GPUs are well-suited architecture for the acceleration of SVM, obtaining up to 15 times sustained speedup compared to its sequential counterpart version.
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Guanjun Wang, Ying Zhao, Minming Tong · Lecture notes in electrical engineering · 2015
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忠幸 榊原 · Medical Entomology and Zoology · 1999
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Peter Brezány, Viera Šipková · Microprocessing and Microprogramming · 1992
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Vivek Kozhikkottu, Swagath Venkataramani, Sujit Dey et al. · 2014
Variations have emerged as one of the most significant challenges facing the design of integrated circuits in nanoscale technologies. As a consequence, variation tolerant design has become essential at all levels of design abstraction.
Cited by 3
Xiaojing Han, Liang Liu, Zhe Zhang et al. · Journal of Physics Conference Series · 2023
Abstract This paper proposes a high performance Vector processor based on the high performance Embedded Core which is named TS800. The TS800 is a 4-core processor based on RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. The traditional CPU mainly supports Scalar calculations, or only supports Vector calculations. For applications such as image and signal processing, there are a large number of data parallel computing operations. To solve the problem of low performance of parallel data calculations in industrial power applications, it is proposed to add VPU hardware implementation in the TS800. The TS800 can support FFT algorithm, adaptive controllers Reinforcement learning and learning-based underlying algorithm requirements. In this paper, the module and data flow between each processing unit and the control circuit, that is, the hardware realization of VPU module are proposed. Large-area units such as float arithmetic, multiplication and division are multiplexed with the Scalar operator in the CPU, while the control circuit is placed in the VPU-ALU, and the area is small. Units such as arithmetic and logic operation instructions, shift operation instructions, comparison operation instructions, and permutation instruction are implemented through the VPU-ALU, which makes the overall design area smaller and the performance better. At the same time, through the fir, fft, conv, matrix, Signal Converge and variance test, it is proved that while executing the same program, the running time of the cpu only with Scalar is 1.44 to 9.55 times that of the CPU with Vector module, which can support the underlying algorithm of the adaptive controller.
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Николай Иванович Дикарев, B. M. Shabanov, Александр Сергеевич Шмелёв · Program systems theory and applications · 2019
В настоящее время резервы в повышении производительности современных процессоров практически исчерпаны, что проявляется в отсутствии роста, как тактовой частоты, так и числа команд, выполняемых в такт, которые определяют скалярную производительность процессорного ядра. В разрабатываемом векторном процессоре с архитектурой управления потоком данных (векторном потоковом процессоре) производительность процессорного ядра может быть повышена до 256 флоп в такт на ядро, что в 8 раз выше по сравнению с последними процессорами Intel Xeon. Это достигается за счет более высокой доли векторных вычислений. В работе показано, что отношение реальной производительности к пиковой на программах битонной сортировки, умножения матриц и 2D Stencil у векторного потокового процессора выше, чем у лучших процессоров традиционной архитектуры.
Cited by 2Open access
ISLAMMD ASHRAFUL, Islam MD Ashraful · Tokyo Tech Research Repository (Tokyo Institute of Technology) · 2023
The FPGA implementation result of multicore (4-core) for different sharing configuration . . . . . . . . . . . . . . .
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Daniel Köhler, Frank Meinl, Holger Blume · Lecture notes in computer science · 2025
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N. Matsubishi, Yu Tokuno, Haruki Mizutani et al. · 2002
The authors describe the implementation and performance of a complex number operation DSP (digital signal processor) LSI for voice pattern matching. The speaker-independent speech recognition system expresses speech data by the root (a complex number) of a transfer function of the vocal tract. The pattern matching in the system revises the differences in the spectrum structure between unknown and reference speech signals in spectrum pattern matching on the frequency axis and performs dynamic programming matching on the time axis simultaneously. The DSP architecture was designed to be able to perform efficient vector and parallel processing on the basis of a cyclic parallel data move processing. The DSP has a performance of 80 MOPS at 60-MHz clock. The chip was fabricated in 1.2- mu m CMOS technology. It has a die size of 74 mm/sup 2/ with approximately 200000 transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Cherniko Alexander V., Cameron B.M., Vixne Pavel E. et al. · Nanoindustry Russia · 2018
NMC NeuroMatrix, RISC- . RISC- , . NMC. , , . NMC , , -, , . NMC . , - . GFLOP/s G/s. , - DDR,
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Wen Jyi Hwang, Sheng-Kai Weng, Ting-Kuan Lin · Journal of the Chinese Institute of Engineers · 2009
Abstract This paper presents a novel hardware architecture for memetic vector quantizer (VQ) design. The architecture uses steady-state genetic algorithm (GA) for global search, and C-Means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state CA operations. It also uses a pipeline architecture for the hardware implementation of C-Means algorithm. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement. Experimental results show that the proposed architecture is an effective method for VQ optimization attaining both high performance and low computational time.
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Jeffrey A. Davis, Ignacio Moreno, Marı́a del Mar Sánchez-López et al. · Optical Engineering · 2023
In this work, we present a method to generate vector beams with a 4f polarization Fourier filtering system that combines a spatial light modulator (SLM) at the input plane and a polarization diffraction grating (PDG) at the output plane. In the Fourier plane, two quarter-wave plates are employed to transform the +1 and −1 diffraction orders onto circular right (RCP) and left (LCP) polarizations, respectively. The PDG at the output plane recombines the two beams producing the colinear superposition of RCP and LCP beams. The application of a random encoding technique to multiplex diffractive elements on the SLM allows the independent encoding of different patterns on the final beam, thus arbitrary vector beams can be generated at the output. Experimental results are included that demonstrate the capability for this approach to encode a variety of polarization vector beams with different topological charges.
Cited by 6Open access
Mireya Paredes Lopez · Research Explorer (The University of Manchester) · 2016
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Lucas Ferreira, Steffen Malkowsky, Patrik Persson et al. · Journal of Signal Processing Systems · 2023
Abstract In computer-vision feature extraction algorithms, compressing the image into a sparse set of trackable keypoints, empowers navigation-critical systems such as Simultaneous Localization And Mapping (SLAM) in autonomous robots, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First, the overall on-chip memory requirements can be lessened, and second, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) dedicated to perform feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) are thoroughly explored to validate the proposed architecture, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures.
Cited by 3Open access
E. Manikandan, K.A. Karthigeyan, K. Immanuvel Arokia James · 2012
Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector co-processor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The FPVC is completely autonomous from the embedded processor(Softcore), exploiting parallelism and exhibiting greater speedup than alternative vector processors. The FPVC supports scalar computation so that loops can be executed independently of the main embedded processor.
Cited by 1
Martin Margala, N.G. Durdle · 2002
This paper describes a gradient vector processor which forms an important part of a shading processor being developed for a high resolution high performance real-time general purpose volume imaging system. The proposed architecture overcomes current image resolution and frame-rate limitations through the use of custom high-speed processors. The gradient vector processor evaluates three arithmetic operations: a square and add operation, square-root, and three division operations. Fully pipelined operation produces a vector every 5 ns or with a 200 MHz frequency at V/sub dd/=3 V and with an accuracy of /spl plusmn/0.78%. The algorithms and implementation in silicon are described in detail.
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Markus Hegland, Paul E. Saylor · International Journal of Computer Mathematics · 1992
The preconditioned conjugate gradient method is well established for solving linear systems of equations that arise from the discretization of partial differential equations. Point and block Jacobi preconditioning are both common preconditioning techniques. Although it is reasonable to expect that block Jacobi preconditioning is more effective, block preconditioning requires the solution of triangular systems of equations that are difficult to vectorize. We present an implementation of block Jacobi for vector computers, especially for the Cray Y-MP/264, and discuss several techniques to improve vectorization. We present these in a progression to show the effect on performance. For the model problem, resulting from a self-adjoint operator, the final implementation of one block Jacobi step uses almost the same amount of time as one point Jacobi step on the Cray Y-MP/264 despite the solution of triangular systems.
Cited by 14
Andreas Bytyn, Rainer Leupers, Gerd Ascheid · arXiv (Cornell University) · 2019
In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e.g. in the well-known ImageNet challenge. As a result, great effort is being put into developing fast and efficient accelerators, especially for Convolutional Neural Networks (CNNs). In this work we present ConvAix, a fully C-programmable processor, which - contrary to many existing architectures - does not rely on a hard-wired array of multiply-and-accumulate (MAC) units. Instead it maps computations onto independent vector lanes making use of a carefully designed vector instruction set. The presented processor is targeted towards latency-sensitive applications and is capable of executing up to 192 MAC operations per cycle. ConvAix operates at a target clock frequency of 400 MHz in 28nm CMOS, thereby offering state-of-the-art performance with proper flexibility within its target domain. Simulation results for several 2D convolutional layers from well known CNNs (AlexNet, VGG-16) show an average ALU utilization of 72.5% using vector instructions with 16 bit fixed-point arithmetic. Compared to other well-known designs which are less flexible, ConvAix offers competitive energy efficiency of up to 497 GOP/s/W while even surpassing them in terms of area efficiency and processing speed.
Cited by 8Open access