Verdú Mulà, Javier · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2008
The evolution of network services is closely related to the network technology trend. Originally network nodes forwarded packets from a source to a destination in the network by executing lightweight packet processing, or even negligible workloads. As links provide more complex services, packet processing demands the execution of more computational intensive applications. Complex network applications deal with both packet header and payload (i.e. packet contents) to provide upper layer network services, such as enhanced security, system utilization policies, and video on demand management.<br/>Applications that provide complex network services arise two key capabilities that differ from the low layer network applications: a) deep packet inspection examines the packet payload tipically searching for a matching string or regular expression, and b) stateful processing keeps track information of previous packet processing, unlike other applications that don't keep any data about other packet processing. In most cases, deep packet inspection also integrates stateful processing.<br/>Computer architecture researches aim to maximize the system throughput to sustain the required network processing performance as well as other demands, such as memory and I/O bandwidth. In fact, there are different processor architectures depending on the sharing degree of hardware resources among streams (i.e. hardware context). Multicore architectures present multiple processing engines within a single chip that share cache levels of memory hierarchy and interconnection network. Multithreaded architectures integrates multiple streams in a single processing engine sharing functional units, register file, fecth unit, and inner levels of cache hierarchy. Scalable multicore multithreaded architectures emerge as a solution to overcome the requirements of high throughput systems. We call massively multithreaded architectures to the architectures that comprise tens to hundreds of streams distributed across multiple cores on a chip. Nevertheless, the efficient utilization of these architectures depends on the application characteristics. On one hand, emerging network applications show large computational workloads with significant variations in the packet processing behavior. Then, it is important to analyze the behavior of each packet processing to optimally assign packets to threads (i.e. software context) for reducing any negative interaction among them. On the other hand, network applications present Packet Level Parallelism (PLP) in which several packets can be processed in parallel. As in other paradigms, dependencies among packets limit the amount of PLP. Lower network layer applications show negligible packet dependencies. In contrast, complex upper network applications show dependencies among packets leading to reduce the amount of PLP.<br/>In this thesis, we address the limitations of parallelism in stateful network applications to maximize the throughput of advanced network devices. This dissertation comprises three complementary sets of contributions focused on: network analysis, workload characterization and architectural proposal.<br/>The network analysis evaluates the impact of network traffic on stateful network applications. We specially study the impact of network traffic aggregation on memory hierarchy performance. We categorize and characterize network applications according to their data management. The results point out that stateful processing presents reduced instruction level parallelism and high rate of long latency memory accesses. Our analysis reveal that stateful applications expose a variety of levels of parallelism related to stateful data categories. Thus, we propose the MultiLayer Processing (MLP) as an execution model to exploit multiple levels of parallelism. The MLP is a thread migration based mechanism that increases the sinergy among streams in the memory hierarchy and alleviates the contention in critical sections of parallel stateful workloads.
Cited by 0Open access
Hesam Zolfaghari, Davide Rossi, Walter Cerroni et al. · IEEE Access · 2020
Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture.
Cited by 17Open access
BOLLA, RAFFAELE, BRUSCHI, ROBERTO · CINECA IRIS Institutial Research Information System (University of Genoa) · 2011
In this paper, we consider energy-aware network\ndevices (e.g. routers, switches, etc.) able to trade their energy\nconsumption for packet forwarding performance by means of\nboth low power idle and adaptive rate schemes. We focus on\nstate-of-the-art packet processing engines, which generally\nrepresent the most energy-starving components of network\ndevices, and which are often composed of a number of parallel\npipelines to "divide and conquer" the incoming traffic load. Our\ngoal is to control both the power configuration of pipelines, and\nthe way to distribute traffic flows among them, in order to\noptimize the trade-off between energy consumption and network\nperformance indexes. With this aim, we propose and analyze a\nconstrained optimization policy, which try to find the best tradeoff\nbetween power consumption and packet latency times. In\norder to deeply understand the impact of such policy, a number\nof tests have been performed by using experimental data from\nSW router architectures and real-world traffic traces.
Cited by 0
Javier Verdú · 2008
The evolution of network services is closely related to the network technology trend. Originally network nodes forwarded packets from a source to a destination in the network by executing lightweight packet processing, or even negligible workloads. As links provide more complex services, packet processing demands the execution of more computational intensive applications. Complex network applications deal with both packet header and payload (i.e. packet contents) to provide upper layer network services, such as enhanced security, system utilization policies, and video on demand management.<br/>Applications that provide complex network services arise two key capabilities that differ from the low layer network applications: a) deep packet inspection examines the packet payload tipically searching for a matching string or regular expression, and b) stateful processing keeps track information of previous packet processing, unlike other applications that don't keep any data about other packet processing. In most cases, deep packet inspection also integrates stateful processing.<br/>Computer architecture researches aim to maximize the system throughput to sustain the required network processing performance as well as other demands, such as memory and I/O bandwidth. In fact, there are different processor architectures depending on the sharing degree of hardware resources among streams (i.e. hardware context). Multicore architectures present multiple processing engines within a single chip that share cache levels of memory hierarchy and interconnection network. Multithreaded architectures integrates multiple streams in a single processing engine sharing functional units, register file, fecth unit, and inner levels of cache hierarchy. Scalable multicore multithreaded architectures emerge as a solution to overcome the requirements of high throughput systems. We call massively multithreaded architectures to the architectures that comprise tens to hundreds of streams distributed across multiple cores on a chip. Nevertheless, the efficient utilization of these architectures depends on the application characteristics. On one hand, emerging network applications show large computational workloads with significant variations in the packet processing behavior. Then, it is important to analyze the behavior of each packet processing to optimally assign packets to threads (i.e. software context) for reducing any negative interaction among them. On the other hand, network applications present Packet Level Parallelism (PLP) in which several packets can be processed in parallel. As in other paradigms, dependencies among packets limit the amount of PLP. Lower network layer applications show negligible packet dependencies. In contrast, complex upper network applications show dependencies among packets leading to reduce the amount of PLP.<br/>In this thesis, we address the limitations of parallelism in stateful network applications to maximize the throughput of advanced network devices. This dissertation comprises three complementary sets of contributions focused on: network analysis, workload characterization and architectural proposal.<br/>The network analysis evaluates the impact of network traffic on stateful network applications. We specially study the impact of network traffic aggregation on memory hierarchy performance. We categorize and characterize network applications according to their data management. The results point out that stateful processing presents reduced instruction level parallelism and high rate of long latency memory accesses. Our analysis reveal that stateful applications expose a variety of levels of parallelism related to stateful data categories. Thus, we propose the MultiLayer Processing (MLP) as an execution model to exploit multiple levels of parallelism. The MLP is a thread migration based mechanism that increases the sinergy among streams in the memory hierarchy and alleviates the contention in critical sections of parallel stateful workloads.
Cited by 4Open access
Reviriego P, Maestro JA, Pontarelli S et al. · IRIS Research product catalog (Sapienza University of Rome) · 2016
Cited by 0
Y. Y. Du, Keyang Chang, Jinglin Shi et al. · 2023
As the Internet of Things becoming widely used, the requirement for high performance network is growing rapidly. Network performance is affected by data transmission based on physical link and packet processing handled by operating system. With the development of network hardware technology and wireless communication technology, network data transmission rate has been further improved, but the packet processing performance based on operating system cannot match it. There are several performance bottlenecks in the traditional packet processing, correspondingly there are various optimization mechanisms to solve these problems and further improve the performance. This paper analyzes some mainstream optimization mechanisms of packet processing based on software. Firstly, we analyze the architecture design of these mechanisms and the workflow when receiving packets. Then we compare the technical methods adopted by each mechanism and problems solved by each mechanism. Finally, we compare the application scenarios and the shortcomings of each mechanism.
Cited by 3Open access
Y. Liu, M.T. Hill, Nicola Calabretta et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2005
We discuss how all-optical signal processing might play a role in future all-optical packet switched networks. We introduce a concept of optical packet switches that employ entirely all-optical signal processing technology. The optical packet switch is made out of three functional blocks: the optical header processing block, the optical memory block and the wavelength conversion block. The operation principle of the optical packet switch is explained. We show that these three functional blocks can be realized by using the nonlinearities of semiconductor optical amplifiers. Some technologies in these three functional blocks are described. The header processor is realized using a Terahertz Optical Asymmetric Demultiplexer. We also describe a header pre-processor to improve the extinction ratio of the header processor output. In the optical memory block, we show that an all-optical memory can be obtained by using two coupled lasers that form a master-slave configuration. The state of the optical memory is distinguished by the wavelength of the master laser. We extend the concept to an optical memory can have multiple states. In the wavelength conversion block, we demonstrate a 160 Gbit/s wavelength conversion using a single semiconductor optical amplifier in combination with a well-designed optical bandpass filter. The semiconductor optical amplifier has a gain recovery time greater than 90 ps, which corresponds to a less than 20 GHz bandwidth for conventional wavelength conversion. We show that by properly using the optical bandpass filter, ultrafast dynamics in the semiconductor optical amplifier can be employed for wavelength conversion at ultrahigh bit-rates.
Cited by 9
Riaan Ingram, F.W. Leuschner, R. Geldenhuys · 2005
We present a method where an optical packet header is not only optically processed, but it is also done by processing each header bit in parallel to further increase the speed of the header recognition and switching in an all-optical node. A three bit parallel processing all-optical switching node based on a symmetric Mach-Zehnder switch was designed and simulated. The packet switch had two inputs and two outputs. The header and payload entered the two inputs separately, and the payload was then switched to one of the two outputs. The header packet was transmitted at a data rate of 10 Gbps and the payload at a data rate of 40 Gbps. It was found that the payload packet would exit both outputs, but at one output it would be suppressed. The measure of success that was used was the output switching ratio (the ratio between the stable optical power of a high bit at the first output and the stable optical power of a low bit at the second output). Switching ratios as high as 12 dB were obtained.
Cited by 0
Qiang Wu, Tilman Wolf · 2008
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing systems on routers employ multiple processor cores. We investigate the design of an efficient run-time management system that handles the allocation of processing tasks to processor cores. Using run-time profiling information about processing requirements and traffic characteristics, the system is able to adapt to dynamic changes in the workload and balance the utilization of all processing resources to maximize throughput. We present a prototype implementation of our system that is based on the Click modular router. Our results show that our prototype system can adapt to changing workloads and process computationally demanding packets at 1.32 times higher data rates than SMP Click.
Cited by 33
Goran Slavic, N. Krajnovic · 2024
Replacement of the vendor routing and switching hardware with the one based on the one driven by the open source software and commodity hardware has been a very interesting prospect especially from the financial side. Work on such solutions often led to partial implementation that did not have all of the features of the vendor router. In this paper is presented solution for software router based on solution using DPDK, VPP, Linux control plane VPP plug-in and Bird software modules. This choice of components enabled the realization of a software router (SR) that overcame the problems of the previous implementations of the SR platforms is dual stack (meaning it supports routing IPv4 and IPv6 traffic in parallel) and able to handle full BGP table.
Cited by 0
Qiongwen Xu, Sebastiano Miano, Xiangyu Gao et al. · arXiv (Cornell University) · 2023
With the slowdown of Moore's law, CPU-oriented packet processing in software will be significantly outpaced by emerging line speeds of network interface cards (NICs). Single-core packet-processing throughput has saturated. We consider the problem of high-speed packet processing with multiple CPU cores. The key challenge is state--memory that multiple packets must read and update. The prevailing method to scale throughput with multiple cores involves state sharding, processing all packets that update the same state, i.e., flow, at the same core. However, given the heavy-tailed nature of realistic flow size distributions, this method will be untenable in the near future, since total throughput is severely limited by single core performance. This paper introduces state-compute replication, a principle to scale the throughput of a single stateful flow across multiple cores using replication. Our design leverages a packet history sequencer running on a NIC or top-of-the-rack switch to enable multiple cores to update state without explicit synchronization. Our experiments with realistic data center and wide-area Internet traces shows that state-compute replication can scale total packet-processing throughput linearly with cores, deterministically and independent of flow size distributions, across a range of realistic packet-processing programs.
Cited by 0Open access
David R. Barach, Leonardo Linguaglossa, Damjan Marion et al. · IEEE Communications Magazine · 2018
In the last decade, a number of frameworks started to appear that implement, directly in userspace with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers, in userspace networking, the flexibility of a modular router (Click and variants), with the benefits provided by techniques such as batch processing that have become commonplace in high-speed networking stacks (such as netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click, where the whole tree is traversed for each packet, in VPP each traversed node processes all packets in the batch (called vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable processing throughput. This article introduces the main VPP concepts and architecture, and experimentally evaluates the impact of design choices (such as batch packet processing) on performance.
Cited by 86
Hiroyuki Yamada · Medical Entomology and Zoology · 2004
Cited by 3
Mihai-Lucian Cristea, Willem de Bruijn, Herbert Bos · Lecture notes in computer science · 2005
Cited by 11
Y. Wang, V. S. Pakki · 2014
The main objective of this Master Thesis is to design and implement a high level synthesis tool for high speed packet processing. For a given network packet, determining the destination and performing the required alterations to the packet are the key parts of Packet Processing. The idea is to provide customers a customized Ethernet switch which is reliable and flexible. As a requirement for this, a high level packet processing language (PPL) is designed instead of any hardware descriptive language because of the regularity of packet processing. The packet processing is described in a powerful way based on the PPL. In this thesis, a design of Ethernet switch based on the PPL is proposed. Hardware implementation is done for the design and MyHDL is used as the hardware description language. Using Python, the compiled PPL program is translated into an hardware model. A tool has been developed which consists of a hardware generator and certain hardware infrastructures. Another part in the thesis is optimization of the initial design. For instance, optimization is done to run as much code as possible in parallel or for removal of unused hardware in the generated switch. Verification is done and synthesis results have been listed comparing the two designs. Hence, we conclude that the initial design is more flexible and has more redundancy while the optimized design is more friendly to hardware cost and power consumption.
Cited by 0
J. W. Schumacher, F. Schreuder, A. Borga et al. · CERN Document Server (European Organization for Nuclear Research) · 2015
Experiments in high-energy physics (HEP) and related fields often impose constraints and challenges on data acquisition systems. As a result, these systems are implemented as unique mixtures of custom and commercial-off-the-shelf electronics (COTS), involving and connecting radiation-hard devices, large high-performance networks, and computing farms. FELIX, the Frontend Link Exchange, is a new PC-based general purpose data routing device for the data-acquisition system of the ATLAS experiment at CERN. Performance is a very crucial point for devices like FELIX, which have to be capable of processing tens of gigabyte of data per second. Thus it is important to understand the performance limitations for typical workloads on modern hardware. We present an analysis of a packet processing algorithm that is used in FELIX, and show how the PC system's memory architecture plays a key factor in the overall data throughput achieved by the application. Finally, we present optimizations that increase the processing throughput by a factor of more than 10x.
Cited by 0Open access
Dai Hyun Kim, Andrew A. Kostrzewski, Sookwang Ro et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2000
This paper describes all-optical packet header processing by content-addressable memory and optical joint transform correlation. The results of proof-of-principle computer simulation and experiment are presented.
Cited by 0
Nicola Calabretta, H.J.S. Dorren · Optical Fiber Communication Conference · 2010
We present a data-format transparent all-optical label processing system suitable for photonic integration that requires N active device to process 2N addresses. We demonstrate error-free all-optical packet switch with label swapping operation at 160 Gb/s.
Cited by 6
Harrick Vin, Jayaram Mudigonda · 2004
In this paper, we describe the vision and the design of a programming environment, called Shangri-La, aimed at making future generations of packet-processing systems – multi-core, light-weight threaded hardware in general, and network processor (NP)-based systems in particular – as easily programmable as today’s workstations and servers. Our environment consists of: (1) a domainspecific programming language for specifying packetprocessing applications, (2) a compiler that incorporates profile-guided techniques for mapping packet-processing applications onto complex packet-processing system architectures, and (3) a run-time system that dynamically adapts resource allocations to create systems that are robust against attacks and that optimize performance and power consumption for the current network conditions. We justify our design and articulate the challenges in designing each of these components. 1.
Cited by 0
Tudor Simion Marian · eCommons (Cornell University) · 2010
Over the past decade, the modern datacenter has reshaped the computing landscape by providing a large scale consolidated platform that efficiently powers online services, financial, military, scientific, and other application domains. The fundamental principle at the core of the datacenter design is to provide a highly available, high performance computing and storage infrastructure while relying solely on low cost, commodity components. Further, in the past few years, entire datacenters have become a commodity themselves, and are increasingly being networked with each other through high speed optical networks for load balancing and fault tolerance. Therefore, the network substrate has become a key component that virtually all operations within and between datacenters rely on. Although the datacenter network substrate is fast and provisioned with large amounts of capacity to spare, networked applications find it increasingly difficult to derive the expected levels of performance. In essence, datacenters consist of inexpensive, fault-prone components running on commodity operating systems and network protocols that are ill-suited for reliable, high-performance applications. This thesis addresses several key challenges pertaining to the communication substrate of the modern
Cited by 2Open access