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About 10,000 papers for “parallel performance analysis”

Performance Analysis of Serial and Parallel Six-Port Modulators

Bin Luo, M.Y.W. Chia · IEEE Transactions on Microwave Theory and Techniques · 2008

We have derived the transfer functions for two types of six-port quadrature phase-shift keying (QPSK) modulators and investigated their performances in terms of carrier leakage, Gray mapping, and conversion efficiencies. Our result shows that the carrier leakage is minimized when Gamma <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = -Gamma <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> . In addition, our analysis reveals here that only the parallel six-port QPSK modulator demonstrates a Gray mapping feature. Our analysis further proves that the serial and parallel modulator give a maximum conversion efficiency of 100% and 50%, respectively, but the efficiency of the serial modulator deteriorates faster than the parallel modulator when the terminations are not ideal. We have also shown that the serial modulator requires tighter design tolerances due to its cascaded topology. Our theoretical and measured results show good agreements with the six-port modulators developed for 4.2 GHz.

Cited by 27

Performance Analysis of Parallel FEM Codes Using TAU Toolkits

Ru Zhong Liang, Min Wang, Hongbo Zhao · 2010

Domain decomposition method is a popular algorithm, which is adopted to the parallel finite element method(FEM). The formulation for solving sparse linear systems of equations is presented. The TAU performance analysis software is used to analyze and understand the execution behavior of the parallel algorithm such as: communication patterns, processor load balance, and computation versus communication ratios, timing characteristics, and processor idle time. This is all done by displays of post-mortem trace-files. Performance bottlenecks can easily be identified at the appropriate level of detail. A large-scale mechanical calculation of a dam by the parallel FEM program was brought out using the Dawning 5000A parallel computer at the Henan technical University Supercomputer Center. The TAU performance analysis software are used to analyze and understand the execution behavior of the parallel algorithm such as: communication patterns, processor load balance, computation versus communication ratios, timing characteristics, and processor idle time. This is all done by displays of post-mortem trace-files. Statistics show that the formulation is efficient in parallel computing environments and that the formulation is significantly faster and consumes less memory.

Cited by 0

Review of Performance Analysis Tools for MPI Parallel Programs

By Shirley Browne, Shirley Browne, Jack Dongarra et al. · 2007

this report are those of the author(s) and should not be construed as an official Department of Defense or National Aeronautics and Space Administration position, policy, or decision unless so designated by other official documentation. Review of Performance Analysis Tools for MPI Parallel Programs

Cited by 0

Design and Performance Analysis of a Parallel Pipeline Robot

Zhonghua Shen, Menglin Xie, Zhendong Song et al. · Electronics · 2024

A parallel four-legged pipeline robot is designed to mitigate the issue of uneven motor loading on the single-leg linkage responsible for movement along the pipe diameter. This issue occurs because the drive motor located closer to the robot body requires higher torque when the serial robot operates along the inner wall of a circular polyethylene gas pipe in an urban environment. The forward and inverse kinematic equations for a single-leg linkage are derived to establish the relationship between joint angles and foot trajectories. Building on this analysis, the forward and inverse kinematic solutions for all four legs are also derived. An optimized diagonal trotting gait is selected as the robot’s walking pattern to ensure a balance between stability and movement efficiency, considering the robot’s structural configuration. Motion simulations for both the serial and parallel robots are performed using simulation software, with a detailed analysis of the displacement of the robot’s center of mass and the leg centers during movement. The driving torque of the leg motors in both configurations is controlled and examined. Simulation results indicate that the designed parallel four-legged pipeline robot achieves lower motion error and smoother leg movements within the pipe. Compared to the serial robot, the maximum torque required to drive the leg motors is reduced by approximately 33%, demonstrating the effectiveness and validity of the overall structural design.

Cited by 4Open access

Analysis of Parallel Multicore Performance on Sobel Edge Detector

Noor Elaiza, Abdul Khalid, Siti Arpah Ahmad et al. · 2014

Abstract:- This paper presents the parallel multicore Sobel edge algorithm which parallelizes the traditional sequential Sobel edge detection algorithm on a parallel multicore platform. The current advancement of multicore architecture can be utilized by the parallel programming paradigm when focuses on the thread operations. The CPUs/cores provide more processing resource to be used but often not fully utilized to its utmost potential. In this paper, the performance of multicore architectures, combined with the parallel communication software named Message Passing Interface (MPI), on the application of Sobel Edge detector algorithm is implemented on various thread processing is performed and analyzed. The test is being done on ten different images with each image tested in the varying size of 1Kx1K, 2Kx2K, and 3Kx3K pixels. The significant performance increment is discovered due to the fact that the CPU is being fully utilized. This proves that the current hardware is far more underutilized than one would expect.

Cited by 0

Protocol and performance analysis of the MPC parallel computer

Olivier Glück, Amal Zerrouki, J.-L. Desbarbieux et al. · 2002

This paper presents the MPC parallel computer and its MPI implementation performed at the Laboratoire LIP6 of Univ. Pierre and Marie Curie, Paris. MPC is a low cost and high performance parallel computer using standard PC main-boards as processing nodes connected through the specific FastHSL board to a high speed communication network using HSL 1 Gbits/s serial links, IEEE 1355 compliant. Two Asics are presented: RCUBE which is the HSL network router and PCI-DDC the network controller implementing the Direct Deposit State Less receiver protocol. The software part of the MPC parallel computer consists of 2 zero-copy layers leading to a latency of 5 to 40 /spl mu/s and a throughput of 490 Mbits/s. An efficient MPI implementation based on MPICH is presented and evaluated on an MPC parallel computer. Measures show a latency of 26 /spl mu/s and an useful throughput of 450 Mbits/s This paper presents also a performances study of the MPI implementation on the MPC computer. This reveals Several possible optimizations to reduce the overall MPI transfer latency on the MPC Computer.

Cited by 5

Performance Analysis of MAC Unit with Various Parallel Adders

Bushra Siddiqui, P. Sudhanya · 2025

The Multiply-Accumulate (MAC) Unit is a crucial component in all DSP Applications, due to its ability to perform high-speed arithmetic operations. This research aims to design and implement an 8-bit MAC Unit capable of performing multiplication and accumulation operations. The MAC Unit employs the same multiplier but integrates different adders such as Kogge-Stone, Ladner-Fischer, Carry Look-Ahead adder, and Ripple Carry Adder. The structures were formed using Verilog Hardware Description Language (HDL) and implemented on Xilinx ISE, with simulation carried out using ModelSim.

Cited by 0

Worst-case performance analysis of parallel, communicating software processes

A. Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel · 2002

In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes. The paper combines a worst-case execution time (WCET) analysis with an analysis of the communication behavior. The communication analysis allows the detection of points, where the program flow of two or more concurrent processes are synchronized. This knowledge allows the determination of the worst-case response time (WCRT). The method does not rely on restrictions on the system design to prevent deadlocks or data loss. Furthermore possible deadlocks and data loss can be detected during the analysis.

Cited by 8

Design and Analysis A High-Performance Parallel Decimal Multiplier

Meesa Ravali, G. Surekha · 2024

This paper presents a novel approach to addressing the demand for efficient decimal arithmetic units in critical applications such as tax calculation, accounting,banking, and currency conversion, with a specific focus on the multiplication operation. The proposed design methodology emphasizes power consumption analysis without compromising performance, decomposing a digit multiplier using techniques inspired by Karatsuba algorithms. The multiplicand and multiplier are partition into various sizes, including multi16-8, multi16-4, multi16-2, and multi16-8-4, and the traditional Ripple Carry Adder (RCA) is replaced with a more efficient Carry Increment Adder (CIA). The study evaluates the designed multipliers using Verilog HDL and the Xilinx ISE tool, analyzing delay, area, and power consumption. The results, based on 16-digit operands, highlight the effectiveness of approach in achieving a balance between computational performance and power efficiency in radix-10 arithmetic units.

Cited by 0

Performance analysis of scheduling techniques in distributed parallel environments

Giulianna Marega Marques, Ricardo José Sabatine, Kalinka Regina Lucas Jaquie Castelo Branco · 2008

The objective of this paper is to offer alternatives of process scheduling and to compare their performances. The environments obtained were considered by applying parallel processing of medical images using the comparison of their performance's time to measure them.

Cited by 2

PERFORMANCE ANALYSIS FOR PARALLEL IMAGE PROCESSING ALGORITHM USING TRANSPUTERS

Sayed F. Bahgat, Said Ghoniemy, Ron Agam · The International Conference on Electrical Engineering/The International Conference on Electrical Engineering · 1998

This paper describes a computable measure that may be used to discriminate between attributes based on configurations of parallel image processing algorithms for achieving optimal system performance. This measure is a compromise between the speed-up factor, the parallelisation efficiency, the number of used transputers, and the complication of the hardware and software algorithm configuration. This measure is described in the context of parallel implementation of digital image processing algorithm for detection of a moving target using a full link transputer

Cited by 0