Search 250 million research papers

Asynchronous Circuit Design

Chris J. Myers · 2001

Cited by 215

Asynchronous circuit applications

Di, Jia, Smith, Scott · CERN Document Server (European Organization for Nuclear Research) · 2020

This book introduces a wide range of existing and potential applications for asynchronous circuits, each accompanied with the corresponding circuit design theory, sample circuit implementations, results, and analysis.

Cited by 0

Asynchronous circuit design - A tutorial

Jens Sparsø · Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU) · 2001

Asynchronous circuits have characteristics that differ significantly from those of synchronous circuits and, as will be clear from some of the later chapters in this book, it is possible exploit these characteristics to design circuits with very interesting performance parameters in terms of their power, performance, electromagnetic emissions (EMI), etc. Asynchronous design is not yet a well-established and widely-used design methodology.There are textbooks that provide comprehensive coverage of the underlying theories, but the field has not yet matured to a point where there is an established currriculum and university tradition for teaching courses on asynchronous circuit design to electrical engineering and computer engineering students.As this author sees the situation there is a gap between understanding the fundamentals and being able to design useful circuits of some complexity.The aim of Part I of this book is to provide a tutorial on asynchronous circuit design that fills this gap.More specifically the aims are: (i) to introduce readers with background in synchronous digital circuit design to the fundamentals of asynchronous circuit design such that they are able to read and understand the literature, and (ii) to provide readers with an understanding of the "nature" of asynchronous circuits such that they are to design non-trivial circuits with interesting performance parameters.The material is based on experience from the design of several asynchronous chips, and it has evolved over the last decade from tutorials given at a number of European conferences and from a number of special topics courses taught at the Technical University of Denmark and elsewhere.In May 1999 I gave a one-week intensive course at Delft University of Technology and it was when preparing for this course I felt that the material was shaping up, and I set out to write the following text.Most of the material has recently been used and debugged in a course at the Technical University of Denmark in the spring 2001.Supplemented by a few journal articles and a small design project, the text may be used for a one semester course on asynchronous design.

Cited by 59Open access

Introduction to Asynchronous Circuit Design

Pallavi Srivastava · 2022

Cited by 6

Accelerated Dual-Path Asynchronous Circuit

Tiben Che, Jingwei Xu, Gwan Choi · IEEE Transactions on Circuits & Systems II Express Briefs · 2015

This brief presents a novel design approach that accelerates an asynchronous circuit system by circumventing transient-fault-induced delays and tolerates latchups and other permanent faults. Specifically, a dual-path asynchronous circuit design and an associated arbiter are developed. Asynchronous circuits inherently tolerate transient errors by incurring an additional delay. This, in turn, can debilitate the circuit to suspend in an environment where the fault rate (FR) is excessively high. The dual-path design approach presented in this brief eliminates this problem by using whichever output or outcome combination becomes valid first from the two asynchronous stages. The design approach is illustrated with a low-density parity-check decoder architecture that must exhibit a high degree of reliability in error-prone operating conditions. Results show that the decoder reduces the delay overhead from 19.5% to 7.5% when the FR is 400/clock cycle. However, the arbiter only introduces about 2% area overhead in addition to the duplication overhead, which is exactly 2X.

Cited by 1

Topics in Asynchronous Circuit Theory.

Janusz Brzozowski · 2006

This is an introduction to the theory of asynchronous circuits -- a survey of some old and new results in this area. The following topics are included: benefits of asynchronous design, gate circuits, Boolean analysis methods, the theory of hazards, ternary and other multi-valued simulations, behaviors of asynchronous circuits, delay-insensitivity, and asynchronous modules used in modern design.

Cited by 2

Designing robust asynchronous circuit components

Siamak Mohammadi, Steve Furber, Jim Garside · IEE Proceedings - Circuits Devices and Systems · 2003

Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.

Cited by 11

State Increment Method of Asynchronous Circuit

Jianshi Tang, Su Tang, YM Wu · ResearchSpace (University of Auckland) · 2008

This paper presents an asynchronous circuit analysis method, the state increment method. A state increment is introduced that takes the clock rising and falling edges as logic variables and into logic operations. The method avoids the checking of the clock state when writing the state transition table. It is therefore simpler, less error prone, and more efficient in analyzing an asynchronous circuit. It can also convert the asynchronous circuit into its synchronous equivalent.

Cited by 0

Capacitor Discharging Through Asynchronous Circuit Switching

Reza Ramezani, Alex Yakovlev · 2013

Operation elasticity due to the proportional relationship between energy and switching activity of asynchronous circuits has made them hugely attractive for energy harvesting systems. Using asynchronous logic makes it possible to minimize the power regulation efforts and instead, supply the circuit directly from the energy storage while a proper load scheduler is employed. In this context, the switching behaviour of the asynchronous load while it is powered by a capacitor becomes crucial to the effectiveness of the scheduler. This paper examines the relationship between the switching behaviour of a self-timed digital circuit and the dynamic characteristic of the voltage on the capacitor while the circuit is powered by the capacitor. For this purpose, a sample system is considered that consists of an initially charged capacitor which is discharged through the switching of a ring oscillator. Closed-form expressions are obtained for the supply voltage of the ring oscillator over time as it operates. Our analytical solution shows maximum 4.6% and 5.4% difference from experimental results in super and sub-threshold regions respectively. The experimental results are captured from a chip fabricated at 180nm technology node.

Cited by 9

Asynchronous circuit synthesis with Boolean satisfiability

Jun Gu, Ruchir Puri · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995

Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a difficult and error-prone task. An adequate synthesis method will significantly simplify the design and reduce errors. In this paper, we present a general and efficient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) specifications. The method partitions a large signal transition graph into smaller and manageable subgraphs which significantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG specifications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 48

Asynchronous circuit synthesis via direct translation

Delong Shang, Fei Xia, Alex Yakovlev · 2003

In asynchronous circuit synthesis, the direct translation method, whereby circuits are derived from Petri net (PN) specifications directly, has not evolved any automatic tools. This paper describes a design method based on direct translation techniques, incorporating refinement, optimization and an automatic tool.

Cited by 15

Petri nets and asynchronous circuit design

Alex Yakovlev · 1996

Can a logic designer build a complex yet efficient asynchronous system completely or almost completely using formal methods and design tools? Is it possible to take a behavioural specification of the system and convert it into logic? What tools are needed and what tools are already available for this purpose? This presentation attempts to answer these and related questions by reviewing recent progress in development of methods and software tools based on Petri nets. Petri nets provide a rare combination of features that are essential in asynchronous circuit design: (i) a simple and easy to understand and manipulate graphical capture; (ii) modelling power that can be adjusted to various types of asynchronous behaviour at different levels of abstraction; (iii) formal operational semantics and verification of various correctness properties of both safety and progress types; (iv) possibility of synthesis of a circuit from its net model. (6 pages)

Cited by 6

Output-determinacy for asynchronous circuit synthesis

Victor Khomenko, Mark Schaefer, Walter Vogler · 2007

Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of non-deterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. We apply the developed theory to improve an STG decomposition algorithm used to tackle the state explosion problem during circuit synthesis, and applied this improved algorithm to some benchmark examples.

Cited by 0

Simulating Asynchronous Parallel Circuit Optimization Algorithms

Árpád Bűrmen, Janez Puhan, Iztok Fajfar et al. · 2013

The idea of asynchronous parallel optimization occured during the efforts to develop efficient parallel optimization algorithms. Since asynchronous parallel algorithms are more difficult to analyse than their synchronous counterparts, the development of such an algorithm benefits greatly from practical experience. The only way to assess the practical value of a particular algorithm is to try it out on established test function suites and real-world problems. In order to test an algorithm it must be implemented and run on a cluster of workstations. Since development and debugging for such platforms is not an easy task, we expect to accelerate the process of developement by utilizing a simulation tool where the developer can concentrate on the algorithm itself without wasting time on various practical implementation issues. We present a simple model of a parallel optimization environment. Based on the model the simulation technique is presented. The simulator is implemented in MATLAB and its use is illustrated with an example. 1

Cited by 0

ATD Circuit for Asynchronous RAM Abstract

Dhaval Patel · 2014

Synchronous design and Asynchronous design are two different types of memory designs. The synchronous design has to suffer from problems such as clock skew, power consumption, synchronization with the external inputs etc. However, an asynchronous memory design responds immediately to any change in any address signal information even if it is due to noise. Thus, it may respond to wrong/unintended address changes and may lead to undesired operations. Address Transition Detection (ATD) circuit provide effective check on this problem by generating a pulse when address information is changed and for that period, the internal circuit of the memory is kept in non-operating mode. This paper deals with description of such ATD circuit and highlights its approach to overcome the enormous behavior of an asynchronous RAM.

Cited by 0

Output-Determinacy and Asynchronous Circuit Synthesis

Victor Khomenko, Mark Schaefer, Walter Vogler · Proceedings · 2007

Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. With our theory we improve an STG decomposition algorithm, which can alleviate state explosion.

Cited by 13Open access

Asynchronous circuit design using Handshake Solutions

A. Peeters, Mark de Wit · 2008

Asynchronous circuit Design is a disruptive technology that is going through a silent revolution. Once deemed an eternal promise of the future, today, hundreds of millions of asynchronous circuits are produced every year, and many of us may use it on a daily basis without being aware of it. Asynchronous circuits may now be found in the vast majority of electronic (biometric) passports, in in-vehicle networks like CAN and LIN, in MEMS-based sensors such as for measuring tire pressure, in access-control systems, and in near field communication devices such as Nokiapsilas 6131 NFC phone.

Cited by 1

An Asynchronous Circuit Design Language (ACDL)

Gregory Martin Bednar, J.H. Tracey · IEEE Transactions on Computers · 1974

This correspondence describes a special purpose Asynchronous Circuit Design Language (ACDL) for specifying the terminal behavior of asynchronous sequential circuits. The language is a valuable tool for formalizing and documenting asynchronous designs, as well as providing a user interface to a completely automated synthesis system. The language includes many special features which permit quick and precise specification of terminal behavior and is best suited for problems that are currently being described informally by word statements.

Cited by 2

SOFT ERROR IN ASYNCHRONOUS CIRCUIT DESIGN

DAYANG NURUL AFIQAH, ABG MOHD TAHIR · Unimas Institutional Repository (Universiti Malaysia Sarawak) · 2019

Soft error considers as a serious concern in state holders as it can cause the circuit to malfunction temporarily. Soft errors are categorised as Single Event Upset (SEU) and Single Event Transient (SET). Radiation actuate soft errors are often happen to most of the electronic products especially with the CMOS technology development. A particle striking on any of the electronic products that can produce soft errors that can be either single event upset or single event transient. Soft errors are not reproducible, and it corrupt the data integrity of the system. This project presents several nodes that are injected with the soft error in the asynchronous circuit. An asynchronous circuit was design using the dual rail encoding and 3-6 code converter while the soft error is represented by using XOR logic gate. The effect of the soft error to the asynchronous circuit is it changed the stored data and it produce errors on the waveform which mean the output parameters are not the same as output parameters. In the project, the presence and absence of error are analysed by observing the output parameter of the waveform that are produced. The software is used to design entry, synthesize the design, compile the schematic diagram, stimulate the gate level schematic of the asynchronous circuit as well as the addition of soft error in the circuit. Moreover, logic gates are commonly used to design the C-element in the software used. The software used to complete the project is Quartus ii Prime Lite edition software.

Cited by 0Open access

Optimization of Asynchronous Sequential Circuit Realizations

D.H. Sawin · IEEE Transactions on Computers · 1974

Tan recently developed a heuristic state assignment algorithm for asynchronous sequential circuits. This note extends Tan's procedure to include optimization of the output state logic, as well as the next state logic, and single-output-change (SOC) flow tables with DON'T CARE entries. The extended algorithm exhibits the same simplicity of execution as Tan's procedure.

Cited by 0