A parallel BCH decoder
Benjamin Arthur Laws · Montana State University ScholarWorks (Montana State University) · 2015
Cited by 1Open access
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About 330 papers for “BCH decoder”
BCH encoder & decoder architectures
Xinmiao Zhang · 2015
Cited by 0
Interpolation-based Chase BCH decoder
Xinmiao Zhang · 2014
BCH codes are adopted in many applications, such as flash memory and optical communications. Compared to hard-decision decoders, the soft-decision Chase BCH decoder can achieve significant coding gain by trying multiple test vectors. Previously, one-pass Chase BCH decoding schemes based on the Berlekamp's algorithm are used to share intermediate results among the decoding trials. In this paper, it will be shown that the interpolation-based one-pass Chase BCH decoder has much lower hardware complexity. Techniques for simplifying the implementation architecture for each step of the interpolation-based decoder are summarized. For a (4200, 4096) BCH code, the interpolation-based Chase decoder with 16 test vectors has 2.2 times higher hardware efficiency than that based on the Berlekamp's algorithm in terms of throughput-over-area ratio.
Cited by 1
An optimal architecture of BCH decoder
Nur Ahmadi, M. Hasan Sirojuddiin, A. Dipta Nandaviri et al. · 2010
An optimal architecture for decoding BCH code is presented in this paper. This design uses a new architecture for syndrome computation to avoid multiplication operation, a Modified Direct Solution Algorithm to reduce the time and area consumption, an inverse error locator polynomial to avoid inverse operation in Chien Search, a new architecture for Chien Search and Error Correction using Finite Field Multiplier (FFM) called power FFM and constant FFM, and a manipulation bit method to reduce the number of XOR gates.
Cited by 5
BCH Encoder and Decoder for Emerging Memories
R Rohith, Abhinav Saji · Journal of Electronics and Informatics · 2021
In this paper, an encoder and decoder system is proposed using Bose-Chaudhuri-Hocquenghem (BCH) double-error-correcting and triple-error detecting (DEC-TED) with emerging memories of low power and high decoding efficiency. An adaptive error correction technique and an invalid transition inhibition technique is enforced to the decoder. This is to improve the decoding efficiency and reduce the power consumption and delay. The adaptive error correction gives high decoding efficiency and invalid transition technique reduce the power consumption issue in conventional BCH decoders. The DEC-TED BCH decoder combines these two techniques by using a specific Error Correcting Code Clock and Flip Flops. This technique provides an error correcting encoder and decoder solution for low power and high-performance application using emerging memories. The design simulated in Xilinx FPGA using ISE Design Suite 14.5.
Cited by 0Open access
BCH CODES DECODER BASED ON EUCLID ALGORITHM
Boris Filippov · SYNCHROINFO JOURNAL · 2021
In the process of algebraic decoding of BCH codes over the field GF(q) with the word length n = qm-1, correcting t errors, both in the time and frequency domains, it is necessary to find the error locator polynomial ?(x) as the least polynomial for which the key equation. Berlekamp proposed a simple iterative scheme, which was called the Berlekamp-Messi algorithm, and is currently used in most practical applications. Comparative statistical tests of the proposed decoder and decoder using the Berlikamp-Messi algorithm showed that they differ slightly in decoding speed. The proposed algorithm is implemented in the environment in Turbo Pascal and can be used for the entire family of BCH codes by replacing the primitive Galois polynomial.
Cited by 0Open access
Low-Complexity Triple-Error-Correcting Parallel BCH Decoder
Jaewoong Yeon, Seung-Jun Yang, Cheol‐Ho Kim et al. · JSTS Journal of Semiconductor Technology and Science · 2013
This paper presents a low-complexity triple-error-correcting parallel Bose?Chaudhuri? Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-bystep (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multiparallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4- parallel (1020, 990) BCH decoder over GF(2<SUP>12</SUP>), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.
Cited by 7
Constant-Time Neural Decoder for some BCH Codes
NTUR (臺灣機構典藏) · 1994
Cited by 0
Software Implementation of Binary BCH Decoder Using Microcontroller
Mohammed Kasim Al-Haddad, Instructor · SHILAP Revista de lepidopterología · 2015
In this paper a decoder of binary BCH code is implemented using a PIC microcontroller for code length n=127 bits with multiple error correction capability, the results are presented for correcting errors up to 13 errors. The Berkelam-Massey decoding algorithm was chosen for its efficiency. The microcontroller PIC18f45k22 was chosen for the implementation and programmed using assembly language to achieve highest performance. This makes the BCH decoder implementable as a low cost module that can be used as a part of larger systems. The performance evaluation is presented in terms of total number of instructions and the bit rate.
Cited by 0Open access
Software Implementation of Binary BCH Decoder Using Microcontroller
Mohammed Al-Haddad · Journal of Engineering · 2015
In this paper a decoder of binary BCH code is implemented using a PIC microcontroller for code length n=127 bits with multiple error correction capability, the results are presented for correcting errors up to 13 errors. The Berkelam-Massey decoding algorithm was chosen for its efficiency. The microcontroller PIC18f45k22 was chosen for the implementation and programmed using assembly language to achieve highest performance. This makes the BCH decoder implementable as a low cost module that can be used as a part of larger systems. The performance evaluation is presented in terms of total number of instructions and the bit rate.
 
Cited by 0Open access
Stochastic Computing based BCH Decoder for WBAN Systems
Kaining Han, Junchao Wang, Warren J. Gross · 2018
BCH codes have been accepted as the error correction coding scheme by the IEEE 802.15.6 standard for wireless body area networks (WBAN). Soft-decision BCH decoders are attractive for the reason that the decoding gains result in significant transmitting energy reduction. An approximate computing technology called stochastic computing is a promising low power and low hardware cost implementation candidate for BCH soft decision decoders. In this paper, a stochastic computing based soft decision decoder is presented for the BCH code defined in the IEEE 802.15.6 standard. According to the evaluation results, the proposed design has the advantages of energy consumption and hardware cost while approaching the decoding performance in terms of block error rate (BLER) compared to existing BCH soft decision decoders. In addition, the proposed design requires no noise power estimation for the soft decision demodulation module, which could further reduce the hardware cost and energy consumption of the WBAN receiver.
Cited by 5
Area efficient parallel decoder architecture for long BCH codes
Yanni Chen, Keshab K. Parhi · 2004
Long BCH codes achieve additional coding gain of around 0.6 dB compared to Reed-Solomon codes with similar code rate used for long-haul optical communication systems. For our considered parallel decoder architecture, a novel group matching scheme is proposed to reduce the overall hardware complexity of both Chien search and syndrome generator units by 46% for BCH(2047, 1926, 23) code as opposed to only 22% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.
Cited by 28
New decoder for double-error-correcting binary BCH codes
Eric Hsueh-Chan Lu, Tofar C.-Y. Chang · IEE Proceedings - Communications · 1996
A step-by-step decoding algorithm is presented for double-error-correcting binary BCH codes of length n = 2m – 1. The decoding algorithm can directly determine whether any received bit is correct or not without knowing the number of errors which have occurred in the received vector and also without determining the corresponding error location polynomial. The merits of the hardware decoder based on the algorithm are that it is very simple and fast. In addition, it is suitable for decoding long block codes.
Cited by 14
A Synthesizable BCH Decoder for DVB-S2 Satellite Communications
Chaves, Cesar G, Lima, Eduardo R De, Mertes, Jacqueline G · 2014
Cited by 0Open access
Fast decoder of BCH code with cyclic decoding method
Evgeniy A. Mytsko, Andrey N. Malchukov, I. Novogilov et al. · 2016
Fast decoder of BCH code (31, 16, 7) which based on matrix algorithm of syndromes computation and parallel data processing was developed. Functional blocks of developed device based on block-based design were described. Device testing with coding and decoding modes and 50 MHz frequency was conducted.
Cited by 1
A Low Power Hard Decision Decoder for BCH Codes
Pranitha Garlapati, B. Yamuna, Karthi Balasubramanian · 2021
In decoding of Bose-Chaudhuri-Hocquenghem codes, Peterson’s algorithm is more efficient for codes with single, double and triple error correcting capabilities. Numerous methods were proposed to reduce the hardware complexity caused due to the inversion operation involved in the Peterson’s algorithm. In this paper, a low complex hardware BCH decoder using inversion-less Peterson’s algorithm presented in literature is designed and its performance is verified with the Matlab results. An attempt is made to design a low power version of this low complex BCH decoder by replacing the parallel Chien search architecture in the decoder with the two-step p-parallel Chien search approach that is originally used in literature with the Berlekamp-Massey Algorithm. For use with the inversion-less Peterson’s algorithm the parallel Chien search architecture has been modified and the resultant decoder has shown a power reduction of up to 42 percentage with a moderate increase in area by 10 percentage.
Cited by 6
Is BCH decoder really necessary in DVB-T2 receiver
Shingchern D. You, Shun-Jie Huang · 2013
The digital video broadcasting-second generation terrestrial (DVB-T2) uses both low-density parity check (LDPC) and BCH error-correction codes. Since the LPDC decoder can correct more errors with more iterations, it is important to know the advantage of using the BCH decoder in a DVB-T2 receiver. This paper addresses this issue and gives some simulation results. The results show that at higher SNR environment, the BCH decoder may not be necessary.
Cited by 0
300 megabit/second Berlekamp decoder for binary BCH codes
C. Kraft · 2002
A very fast, parallel, combinatorial Berlekamp decoder that can perform the second step in binary BCH decoding at rates exceeding 300 Mb/s is presented. The circuit given is for the t=3 case. It is possible to build a t=5 decoder that can operate faster than 100 Mb/s. In addition to the Berlekamp section, the complete BCH decoder also requires a syndrome generator and a root finder. These can be implemented in a straightforward way with sequential circuits and ROMs or fast static RAMs. For the t=3 code, there are only three syndrome components yielding 48 clock cycles for 255 incoming bits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 1
An Area Efficient (31, 16) BCH Decoder for Three Errors
M. Prashanthi, P. Samundiswary · International Journal of Engineering Trends and Technology · 2014
Cited by 2
An enhanced decoder for multiple-bit error correcting BCH codes
Hupo Wei, Xiaole Cui, Qiang Zhang et al. · 2015
With the advancement of device technology and decreasing the gap of memory cells, radiation particles may upset more multiple adjacent memory cells, and conventionally used BCH code in SRAM needs an improvement to correct the multiple bit soft errors. This paper proposes a novel high-speed BCH decoder that corrects triple-adjacent, double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than adjacent errors, the syndrome computation depend on the number of errors. The decoder has been implemented with a 130nm CMOS technology, and experimental results show that the proposed decoder incurs almost the same power and area overhead as compared to the conventional TEC BCH code serial decoder which corrects any double-bit errors in serial. What is more, the delay overheads incurred by the proposed parallel decoder is 50% lower than the serial decoder.
Cited by 2