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About 2,399 papers for “Backplane”

Backplane Device

National Cancer Institute · Definitions · 2020

Ope n Pe e r Re v ie w on Qe ios

Cited by 0Open access

Section 3- Backplane Architecture Backplane Designer’s Guide

2002

The primary criteria for backplane design are low cost, high speed, and high reliability. To attain these often-conflicting goals, it is necessary to maximize the performance of every aspect of the design, including the backplane configuration. A prime consideration is how data is transmitted between the driver and receiver(s), and data transmission depends of on three backplane characteristics: 1. The distance or space between the sending and receiving devices 2. The speed at which data must be sent to a receiving device 3. The capacitive loading the signal will see traveling between the driver and receiver(s) When constructing a backplane, the designer has to make several choices with regard to connectivity, topology, and timing architecture. Connectivity refers to data transmission, and specifically to whether data is transmitted in parallel across multiple lines or in a serial stream. Topologies are the different methods for configuring a backplane layout: point-to-point, multidrop, and multipoint. Timing architecture refers to the choice between synchronous, source-synchronous, or asynchronous signal interfaces. Because all these options have strengths and weaknesses, the final design choices depend on the requirements the backplane must meet. Section Reference This section presents information covering:

Cited by 0

Section 2- Backplane Protocols Backplane Designer’s Guide

2002

Backplane bus protocols determine- electrically and mechanically- how signals are dropped off or picked up at every device attached to the line. Protocols determine how cards pass information, the speed of data transfer, the maximum number and type of peripheral devices allowed, and the physical size and layout of the system. In general, the choice of the correct protocol for a backplane design is a complex decision that involves many design compromises. No one solution will give the best performance in each design category. This section discusses the readily available Peripheral Component Interconnect (PCI)-based and VERSAmodule Eurocard (VME)-based backplane protocols. The goal of this section is to provide an understanding of what is necessary to implement a backplane protocol and how to choose the protocol that best fits the design needs. Section Reference This section presents the following information: • A summary comparison of PCI-based and VME-based protocols • A comparison, by feature, of the strengths and weaknesses of each protocol

Cited by 0

backplane and

X. Ye, J. Nadolny, J. L. Drewniak et al. · 2016

Cited by 0

LOAF_x04 Backplane

Joshua M. Pearce, Shane Oberloier, Nicholas Whisman et al. · OSF Preprints (OSF Preprints) · 2024

Cited by 0

Section 4- Backplane Design Considerations Backplane Designer’s Guide

2002

This section focuses on designing high-performance parallel backplanes, a task that can be extremely complex. To assure high performance and good signal integrity, many issues must be considered during the design process. To a large extent, system requirements will define backplane design, determining if distributed capacitance effects will be present on the backplane. Due to the frequencies of high-performance backplanes, transmission line behavior is common in most applications. For backplane design, the minimum system requirements are backplane frequency, the number of loads, and, assuming a multidrop/multipoint configuration, the number of outputs switching. Section Reference This section presents information covering: • Backplane layout and design parameters • Distributed capacitance • Transmission line effects • Impedance • I/O device capacitance • Stub effects

Cited by 0

Section 7- Backplane Transceiver Technologies Backplane Designer’s Guide

2002

integrated circuit manufactures supply transceiver technologies that are designed primarily for backplanes with specific parameters in mind. One device technology might focus on low power consumption and another on high speed. There are also technologies that try to offer a complete solution by addressing each and every backplane issue. A large part of backplane design is focused on which device technology best suits the design. This section serves as a guide to choosing among the following backplane transceiver technologies:

Cited by 0

Fastbus backplane impedance

M. Haldeman · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1982

None

Cited by 0Open access

Reconfigurable Backplane Topology

Rajendra Prasad, Gunda, Ajay Kumar, Thenmatam, Srinivasa Rao, Kurapati · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2006

In the field of embedded computer and communication systems, the demands for the interconnection networks are increasing rapidly. To satisfy these demands much advancement has been made at the chip level as well as at the system level and still the research works are going on, to make the interconnection networks more flexible to satisfy the demands of the real-time applications. This thesis mainly focuses on the interconnection between the nodes in an embedded system via a reconfigurable backplane. To satisfy the project goals, an algorithm is written for the reconfigurable topology that changes according to the given traffic specification like throughput. Initially the connections are established between pairs of nodes according to the given throughput demands. By establishing all the connections, a topology is formed. Then a possible path is chosen for traversing the data from source to destination nodes. Later the algorithm is implemented by simulation and the results are shown in a tabular form. Through some application examples, we both identify problems with the algorithm and propose an improvement to deal with such problems.

Cited by 0Open access

Backplane API Gateway

Martín Serrano, Achille Zappa, Waheed Ashraf et al. · River Publishers eBooks · 2024

Cited by 0

User Logic Backplane

Deskew Fsm · 2010

The RXAUI standard was developed as a means to improve the 10-Gigabit Ethernet port density. The number of XAUI interfaces that could be implemented was limited by the number of available transceivers, with capacity and performance still to be utilized. RXAUI halves the number of transceivers required compared with a XAUI implementation. RXAUI is a two-lane, 6.25 Gbps-per-lane serial interface. It is intended to work with an existing XAUI implementation and multiplexes/demultiplexes the two physical RXAUI lanes into 4 logical XAUI lanes. Each RXAUI lane is a differential pair carrying current mode logic (CML) signaling, and the data on each lane is 8B/10B encoded before transmission. The Dune Networks RXAUI implementation maintains 8B/10B disparity per RXAUI physical lane and the Marvell RXAUI implementation maintains 8B/10B disparity per XAUI logical lane. Special code groups are used to allow each lane to synchronize at a word boundary and to de-mux the two physical RXAUI lanes into four logical XAUI lanes at the receiving end. For full details on the RXAUI specification, contact Dune Networks or Marvell. Applications The applications of RXAUI have extended beyond 10-Gigabit Ethernet to backplane and other general high-speed interconnect applications. Figure 1 shows a typical backplane application.

Cited by 0

Optical backplane interconnect

PAYNE ROGER ALYN, MACKENZIE FIONA, HODGSON MICHAEL JOHN · Institutional Repository of Xi'an Institute of Optics and Fine Mechanics, Chinese Academy of Sciences (Xian Institute of Optics and Precision Mechanics) · 2008

An optical backplane interconnect comprises a backplane comprising parallel D-fibres (1) that form an optical bus embedded in a plastics substrate (15), which form a coupling with respective parallel D-fibres (23) at an angle .PHI. in a connecting block (21) that is mounted on a card (2). Circuit components on the card are connected by optical fibres (9) to the fibres in the connecting block. The card is held by connections (18, 19), and as the card is pushed into position, coupling means, comprising balls (25, 26) on the connecting block, self-aligns in groove (27) on the blackplane, to set the angle .PHI. between the fibres, to provide a controlled, reliable optical coupling.

Cited by 0

High-speed backplane connectors

Howard Johnson · 2011

Printed circuit board (PCB) backplanes and backplane connectors form the cornerstone of many large system architectures, particularly in the fields of communication and high-performance computing. This paper investigates the limits to the electrical performance of backplane connectors. It discusses the main factors affecting performance, and predicts the future of backplane connector development.

Cited by 5

Heuristics for Backplane Ordering

James P. Cohoon, Sartaj Sahni · Libra · 1985

The Board Permutation Problem, a backplane ordering problem, has been previously shown to be NP - hard. We develop here several heuristics for the Board Permutation Problem. These heuristics produce solutions that are locally optimal with respect to some nontrivial transforms. The heuristics are analytically shown to be m/3- approximate, where m is the number of nets in a problem instance. The heuristics have been shown experimentally to have quite acceptable behavior. Several of the heuristics make use of a Statistical Mechanics technique (simulated annealing) for thermal equilibrium analysis in producing their solution. Note: Abstract extracted from PDF file via OCR

Cited by 9Open access

Olympus System Backplane Definition

Pierre‐Yves Le Bas · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2022

The purpose of this document is to define the backplane of the Olympus firing system, a modular system based on SpaceWire communication between modules. The backplane provides the connection between the modules, controller (embedded in the front module), the SpaceWire router, and an alternative switch. Those connections include SpaceWire links, interlocks, a key, a dead-man switch (DMS)/charge, timing lines, power distribution, geographical addresses, and communication to the human-machine interface (HMI). This backplane is based on the VMEBus International Trade Association (VITA) 46 Specification (VPX) and OpenVPX standards for a 3U backplane. Unless otherwise specified, those standards apply for signal definitions and mechanical specifications.

Cited by 0Open access

Practical Analysis of Backplane

Lambert Simonovich, Backplane Specialist · 2009

Accurate, verified models for vias in a multilayer circuit board are necessary to predict link performance in the GHz regime. This paper describes the methodology of using measurements on a test vehicle to build a high bandwidth, scalable model of long vias which includes the through and stub effects which can be used for system simulation. This simple model also provides valuable insight into the root cause of performance limits and how to overcome them.

Cited by 0

AM backplane for AMOLED

Mk Han, Min-koo Han · 2015

Abstract: Active matrix organic light emitting diode (AMOLED) displays are considerably attractive for high brightness, high efficiency and fast response time. Active matrix employing thin Film Transistors (TFTs) allows OLED displays to be larger in size, higher in resolution and lower in power consumption than passive matrix. Especially, low temperature polycrystalline silicon (LTPS) TFT employing excimer laser annealing (ELA) is widely used due to high mobility and high stability. A number of TFT active matrix pixel circuits have been developed in order to compensate for TFT parameter variations due to the fluctuation of excimer laser energy. We discuss various compensation schemes of LTPS TFT pixel circuits.

Cited by 0