Sangook Moon · 2005
The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the top level of GF (Galois field) multiplication and GF division, has been the double-and-add algorithm, which is being recently challenged by the NAF (non-adjacent format) algorithm. In this paper, we propose a more efficient and novel approach of a scalar multiplication method than existing double-and-add by applying redundant recoding which originates from radix-4 Booth's algorithm. We call the novel algorithm quad-and-add. After deriving the algorithm, we created a new GF operation, named point quadruple, and verified it with calculations of a real-world application. The derived numerical expressions were verified using both C programs and HDL (hardware description language). The proposed method can be utilized in many elliptic curve security applications for handling efficient and fast calculations.
Cited by 6
Ravi Teja Reddy Levaka · 2011
With the rapid increase of small devices and its usage, a better suitable security providing mechanism must be incorported keeping the resource constraints of the
devices in mind. Elliptic Curve Cryptography (ECC) serves the best and highly suitable for wireless sensor Networks (WSN) in providing security because of its smaller key size and its high strength of security against Elliptic Curve Discrete Logarithm Problem (ECDLP) than any other public-Key Cryptographic Systems. But there is a scope to reduce key calculation time to meet the potential appli-
cations, without compromising in level of security in particular for wireless sensor networks. Scalar Multiplication is the costliest operation among the operations in Elliptic Curve Cryptography which takes 80% of key calculation time on WSN motes. This research proposes an algorithm based on Booth's Encoding Pattern,
o®ering minimal Hamming Weight and signi¯cantly reduces the computational cost of scalar multiplication. Simulation results has proved that the Booth's en-coded pattern performs better over the existing techniques if there are atleast 46% number of 1's in the key on an average.
Cited by 0
Guangpu Guo, Mohammad Ashtijou · 2002
Booth's multiplication algorithm and its modified version are reviewed (A.D. Booth, 1990). It is shown that high radix Booth's multiplication needs a correction cycle only when fixed point fractions are used. The correction cycle with [(n-1) mod log/sub 2/(r)] arithmetic right-shifts is not for the integer case.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 2
John M. Anderson, B. Troutman, R.A. Allen · 1982
Two 2μ CMOS LSI chips with multiply times less than 100ns, and dissipation of 150mW, will be discussed. The use of Booth's algorithm speeds the multiplication process since the multiplier word is essentially recoded into 8 digits.
Cited by 5
Somnath Bandyopadhyay, Saikat Basu, A. K. Choudhury · IEEE Transactions on Computers · 1972
A simple method for the implementation of Booth's algorithm for multiplication of signed binary numbers has been presented. It has been shown that for large word lengths, a significant economy has been achieved compared to Majithia and Kitai's method.
Cited by 7
Nilay Nagdeve, Vishal Moyal, Archana Fande · 2012
In this paper, a comparison between different compressors is presented. A proper compressor selection approach to get minimum XOR delay is also shown. Again Booth's Modified Algorithm can be use for signed multiplication to get reduced partial products after which these compressors or a network of compressors can be used. This paper will help to choose a proper compressor for higher multiplication.
Cited by 1
Chiou‐Yng Lee, Yu-Hsin Chiu · 2006
A new algorithm forthemultiplication oftwo elements inGF(2m)basedonthemodified Booth's algorithm is presented. Theproposed algorithm permits efficient realization ofthemultiplexer-based bit-parallel multiplication using iterative arrays. Thelatency ofthemultiplier has3m/2clock cycles. For theestimated complexity oftheproposed multiplier, wetakeinto thetransistor countusing astandard CMOS VLSIrealization. Ouranalysis showsthat, intermsofthetimeandthespace complexities, themultiplexer-based arrayarchitecture isthe better choice forourproposed bit-parallel systolic multiplier. KeywordsBooth's algorithm, bit-parallel systolic multiplier
Cited by 0
S. Rooban, M. Nagesh, M V S L Prasanna et al. · 2021
A description of the multiplication of two binary numbers of size 128-bits each using Radix-4 Booth's Algorithm is presented in this paper. Booth Encoder circuit, Partial Product Generator tree, and Carry save adders are the main building blocks of any Booth Multiplier. Carry Save Adder is useful for adding all the partial products that are obtained. The radix-4 Booth algorithm is used to decrease the partial products which are generated intermediately. Higher representation radix results in smaller amounts of digits for a number to be represented. Radix-4 algorithm of booth helps to reduce the partial products when compared to Radix-2 booth's algorithm by a factor of half. Radix- 4 booth's algorithm is recommended because most of the parameters performances such as delay, area and power are more efficient for the radix-4 algorithm when compared to the higher radices (like radix-8's booth's algorithm or radix-16 booth's algorithm). Partial products are minimized by using the radix-4 algorithm, as a result, the area is reduced to very minimum value. The smaller area obtained implies that the boothmultiplier used is more effective in terms of area, that implies, the delay is smaller. Speed of the multiplier is higher if delay is smaller. Simulation analysis prove that proposed radix-4 multiplier based designs are more efficient if the multiplier is 64 & 128 bits. The proposed design of radix-4 128-bit Booth Multiplier is implemented using Xilinx Vivado software.
Cited by 7
E. Delhaye, C. Rocher, Marc Fichelson et al. · 1987
A 8 × 8 parallel multiplier, operating in 2's complement mode, is described. Tne circuit, implementing the modified Booth's algorithm, uses both E/R DCFL and transfer logic cells. The best multiplication time measured on fabricated chips is 3 ns, which corresponds to 115 ps average gate delay. The associated power consumption is 330 mW.
Cited by 2
Karwan Javanmardi, Sobhan Sofimowloodi, Amir Attar et al. · 2024
This paper discusses the improvement of the multiplication operation speed in multipliers based on Booth's algorithm. The main goal of Booth's algorithm is to reduce the number of partial products by half, as a result of which, the multiplication operation will be completed sooner. The method proposed in this paper to solve this problem is designing a parallel multiplier using only one Booth Encoder circuit and one adder circuit. With the help of a series of circuits and control signals, these two circuits work in parallel and simultaneously so that the speed of the multiplication operation is not affected much. The production of partial products and their accumulation is being done in parallel. At the same time, the amount of hardware that is directly related to the power consumption is significantly reduced. The presented design is implemented in CMOS technology and 0.18um process. The proposed multiplier produces the correct output after 78nsec, and its operating speed is 12.8 MHz. The average power consumption of this multiplier is approximately 1.09 mW, and the number of transistors required for its construction is 2927.
Cited by 1
Leidiane Silva Caldeira, Tales Cleber Pimenta, Evandro Daniel Calderaro Cotrim · 2003
This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.
Cited by 0
Jinhua Hong, Cheng‐Wen Wu · 2002
We propose a radix-4 modular multiplication algorithm based on Montgomery's algorithm, and a radix-4 cellular-array modular multiplier based on Booth's multiplication algorithm. The radix-4 modular multiplier can be used to implement fast RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than the cellular-array modular multiplier based on the original Montgomery's algorithm. The time to calculate a modular exponentiation is about n/sup 2/ clock cycles, where n is the word length, and the clock cycle is roughly equal to the delay time of a full adder. The utilization of the multiplier is 100% by interleaving consecutive exponentiations. Locality, regularity, and modularity make the proposed architecture suitable for VLSI implementation.
Cited by 1
Y. Oowaki, Kenji Numata, Kenji Tsuchiya et al. · IEEE Journal of Solid-State Circuits · 1987
A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.
Cited by 24
Kuo-Hsing Cheng, Yu-Kwang Yeha, Farn-Sou Lian · 2002
A 16/spl times/16-bit parallel multiplier fabricated in a 1.0 /spl mu/m BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 /spl mu/W at 2.5 V supply voltage operation.
Cited by 2
Seyed Saleh Ghoreishi, Mohammad Ali Pourmina, Hamed Bozorgi et al. · 2009
Rivest, Shamir and Adleman (RSA) encryption algorithm is one of the most widely used and popular public-key cryptosystem. The main step in this algorithm is modular exponentiation which can be done by a sequence of modular multiplication. Thus, modular multiplication is the major factor, in many cryptosystems, e.g. the RSA Two-Key system and in the proposed digital signature standard DSS. One of the most efficient algorithms of modular multiplication is the Montgomery multiplication. In this paper, modified radix-4 modular multiplication was developed based on Booth's multiplication technique. We use CSA (Carry Save Adder) to avoid carry propagation. Also a very fast algorithm was presented and used for computing the modular reduction. We proposed new hardware architecture for optimum implementation of this algorithm. According to our design, for encrypting an n-bit plaintext, we need to about 3/4n (n + 11) clock cycles. We used Xilinx VirtexII and XC4000 series FPGAs (Field Programmable Gate Array). As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 15ms and 50ms at 54.6MHz and 16.1MHz on Xilinx VirtexII and XC4000 series FPGA, respectively. Finally we compared our results with the previous works. We can say that a significant improvement was achieved in terms of time and in terms of used time-area (TA) our work is good.
Cited by 22
E. Delhaye, C. Rocher, Jean-Claude Baelde et al. · IEEE Journal of Solid-State Circuits · 1987
The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.
Cited by 3
Laili Erni, Hitam · University of Malaya Students Repository · 2003
The Pipelined Multiplier Accumulator has brought many approaches and changes to the conventional MAC. The Pipelined MAC is believe can speed up the operations of the previous conventional MAC plus it can reduce the time and cost. The effectiveness of pipelining concept in the system's implementation is undeniable as the performance of the system is improved where the multiplication process is pipelined with the addition process. Pipelining reduces cycle time but does not reduce the total time required for multiplication. One way to speed up multiplication is Booth Algorithm, which perform several steps of the multiplication at once. Booth's algorithm takes advantage of the fact that an adder-subtractor is nearly as fast and small as a simple adder. The implementation of Accumulator using Carry Look-ahead Adder (CLA) technique has brought to fast operation achieved in addition process of 8-bit data. The pipeline MAC is designed to increase the speed of MAC operations, decrease the cycle time and to avoid the delay in the conventional MAC.
Cited by 0
Ram Racksha Tripathi, Prakash S.G · International Journal of VLSI Design & Communication Systems · 2016
Multiplication is a crucial function and plays a vital role for practically any DSP system. Several DSP algorithms require different types of multiplications, specifically modified booth multiplication algorithm. In this paper, a simple approach is proposed for generating last partial product row for reducing extra sign (negative bit) bit to achieve more regular structure. As compared to the conventional multipliers these proposed modified Booth's multipliers can achieve improved reduction in area 5.9%, power 3.2%, and delay 0.5% for 8 x 8 multipliers. We can also observe that achievable improvement for 16 x 16 multiplier in area, power, delay are 4.0%, 2.3%, 0.3% respectively. These multipliers are implemented using verilog HDL and synthesized by using synopsis design compiler with an Artisan TSMC 90nm Technology
Cited by 2Open access
Mamtha Prajapati Mamtha Prajapati · IOSR Journal of VLSI and Signal processing · 2013
Fast multipliers are essential components of most VLSI applications like digital signal processing systems, microprocessors, etc. The speed of multiplier operation is of fastidious importance within the generalpurpose processors. The essential multiplication principle is twofold i.e., Evaluation of partial product and accumulation of the shifted partial products with the motivation to Booth's algorithm. In this pithy, an efficient design of modified Booth Encoder and Decoder scheme for high performance of parallel multiplier has been proposed. The proposed Booth encoder and Decoder logic are competitive with the present schemes and shows enhancements in delay. It additionally shows a substantial reduction in area.
Cited by 1Open access
Neeta Pandey, Saurabh Gupta · International Journal of Image Graphics and Signal Processing · 2015
The paper presents a design scheme to provide a faster implementation of multiplication of two signed or unsigned numbers. The proposed scheme uses modified booth's algorithm in conjunction with barrel shifters. It provides a uniform architecture which makes upgrading to a bigger multiplier much easier than other schemes. The verification of the proposed scheme is illustrated through implementation of 16x16 multiplier using ISIM simulator of Xilinx Design Suite ISE 14.2. The scheme is also mapped onto hardware using Xilinx Zynq 702 System on Chip. The performance is compared with existing schemes and it is found that the proposed scheme outperform in terms of delay.
Cited by 1Open access