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About 2,776 papers for “CPU cache”
Laura Grigori, Inria Saclay, B. Ghosting · 2016
Algorithms spend their time • in doing useful computations (flops) • or in moving data • between different levels of the memory hierarchy • and between processors
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SpringerReference · 2011
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Ling Liu, M. TAMER ÖZSU · Encyclopedia of Database Systems · 2009
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Peřina, Daniel · Brno University of Technology Digital Library (Brno University of Technology) · 2022
Cílem této práce je navrhnout a implementovat simulátor činnosti vyrovnávací paměti procesoru. Protože v dnešních počítačích je řádový rozdíl mezi výkonem procesoru a hlavní paměti je nutné používat vyrovnávací paměti jako mezivrstvu. Simulátor má vizuálně demonstrovat vliv těchto pamětí na různých algoritmech a problémy, které se mohou vyskytnout při jejím nevhodném využití. Pro jednoduché použití je simulátor implementován jako webová aplikace pomocí frameworku Vue.js. Aplikace umožňuje zadat assembler kód a ten poté vykonat na různých typech vyrovnávací paměti. Aplikace vizualizuje tok dat mezi vyrovnávací a hlavní pamětí. Pro simulátor byly také vytvořeny ukázkové programy, které předvádějí různé vlastnosti a problémy vyrovnávacích pamětí. Díky této aplikaci je možné názorně předvést význam těchto pamětí.
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Mark Hayter, Derek Mcauley · 1994
This paper discusses the use of the CPU cache when the processor is being used to manipulate stream data, in particular isochronous media such as as video. The principal idea is to enable data to avoid main memory and flow directly into a portion of the cache. When used with a "cache aware" operating system this method is shown to provide a rich support environment for multimedia manipulation. Experiments to demonstrate this have been performed on a workstation based on the Desk Area Network architecture, and results are presented. 1 Introduction Multimedia research in the last few years has concentrated on transporting isochronous data across the network and through the workstation while retaining the real-time characteristics to enable smooth display. However, the next range of multimedia applications will be those that do more than just present the data to a human user. They will require some processing to be done on the arriving streams in addition to, or instead of, simply passin...
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Jan Holub · Acta Polytechnica · 2007
The finite automata are mathematical models for finite state systems. More general finite automaton is the nondeterministic finite automaton (NFA) that cannot be directly used. It is usually transformed to the deterministic finite automaton (DFA) that then runs in time O(n), where n is the size of the input text. We present two main approaches to practical implementation of DFA considering CPU cache. The first approach (represented by Table Driven and Hard Coded implementations) is suitable forautomata being run very frequently, typically having cycles. The other approach is suitable for a collection of automata from which various automata are retrieved and then run. This second kind of automata are expected to be cycle-free.
Cited by 3Open access
Tomaž Hočevar (3738016), Janez Demšar (3738019) · Figshare · 2017
Cited by 0Open access
Mani Tofigh, Edward Guo, Weiwei Jia et al. · ArXiv.org · 2025
This paper shows that cache-based optimizations are often ineffective in cloud virtual machines (VMs) due to limited visibility into and control over provisioned caches. In public clouds, CPU caches can be partitioned or shared among VMs, but a VM is unaware of cache provisioning details. Moreover, a VM cannot influence cache usage via page placement policies, as memory-to-cache mappings are hidden. The paper proposes a novel solution, CacheX, which probes accurate and fine-grained cache abstraction within VMs using eviction sets without requiring hardware or hypervisor support, and showcases the utility of the probed information with two new techniques: LLC contention-aware task scheduling and virtual color-aware page cache management. Our evaluation of CacheX's implementation in x86 Linux kernel demonstrates that it can effectively improve cache utilization for various workloads in public cloud VMs.
Cited by 0Open access
Jesus Alonso Ortiz Lanzziano · Universidad Industrial de Santander · 2016
El siguiente trabajo de investigación presenta un análisis y una mejora de desempe˜no del algoritmo de Migración Reversa en Tiempo (RTM) 3D desarrollado por el grupo de investigación CPS, implementado sobre unidades de procesamiento central o CPU. La mejora hace referencia a una disminución del tiempo de ejecución, disminución de la cantidad de accesos a memoria caché y una mejor utilización de los recursos de la CPU. Se usó la interfaz de programación OpenMP, la cual permite distribuir la ejecución del algoritmo entre todos los nícleos de los que dispone una CPU. La toma de tiempos y la evaluación propia de la ejecución se hace con herramientas de software del lenguaje de programación C y del sistema operativo GNU/Linux. La obtención de estos datos permite registrar, tabular y visualizar los resultados del algoritmo original y el desarrollado con OpenMP. Para la realización del trabajo se partió de una implementación base secuencial, se identificaron las secciones paralelables del algoritmo, se mejoró el acceso a memoria caché y se agregaron las directivas de OpenMP. Se realizaron varias pruebas en diferentes sistemas de cómputo de las cuales se hace un análisis y una evaluación de los resultados obtenidos.
Cited by 0Open access
Viraj Mankad, Virag Shah, Sachin Gajjar et al. · Communications in computer and information science · 2023
Cited by 1
Jakob Balkovec · Zenodo (CERN European Organization for Nuclear Research) · 2026
This release contains the code, datasets, and paper for the study: "Do Powerful CPUs Reduce the Need for Efficient Code?" The project evaluates two performance factors: Algorithmic complexity (Bubble Sort vs std::sort) Cache locality (row-major vs column-major traversal) The repository includes all benchmark implementations, generated datasets, analysis scripts, and the final paper. The work was written as my acceptance essay for the Master's program in Data Engineering and Analytics at the Technical University of Munich (TUM).
Cited by 0Open access
Alan Jay Smith · IEEE Transactions on Computers · 1987
The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function of line size is examined carefully through the use of trace driven simulation, using 27 traces from five different machine architectures. The change in cache miss ratio as the line size varies is found to be relatively stable across workloads, and tables of this function are presented for instruction caches, data caches, and unified caches. An empirical mathematical fit is obtained. This function is used to extend previously published design target miss ratios to cover line sizes from 4 to 128 bytes and cache sizes from 32 bytes to 32K bytes; design target miss ratios are to be used to guide new machine designs. Mean delays per memory reference and memory (bus) traffic rates are computed as a function of line and cache size, and memory access time parameters. We find that for high performance microprocessor designs, line sizes in the range 16-64 bytes seem best; shorter line sizes yield high delays due to memory latency, although they reduce memory traffic somewhat. Longer line sizes are suitable for mainframes because of the higher bandwidth to main memory.
Cited by 198
Hao Wen, Wei Zhang · 2019
Unlike the traditional CPU-GPU heterogeneous architecture where CPU and GPU have separate DRAM and memory address space, current heterogeneous CPU-GPU architectures integrate CPU and GPU in the same die and share the same last level cache (LLC) and memory. For the two-level cache hierarchy in which CPU and GPU have their own private L1 caches but share the LLC, conflict misses in the LLC between CPU and GPU may degrade both CPU and GPU performance. In addition, how the CPU and GPU memory requests flows (write back flow from L1 and cache fill flow from main memory) are managed may impact the performance. In this work, we study three different cache requests flow management policies. The first policy is selective GPU LLC fill, which selectively fills the GPU requests in the LLC. The second policy is selective GPU L1 write back, which selectively writes back GPU blocks in L1 cache to L2 cache. The final policy is a hybrid policy that combines the first two, and selectively replaces CPU blocks in the LLC. Our experimental results indicate that the third policy is the best of these three. On average, it can improve the CPU performance by about 10%, with the highest CPU performance improvement of 22%, with 0.8% averaged GPU performance overhead.
Cited by 5
Erion Çano · Advances in intelligent systems and computing · 2014
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Vlad Mihai Mihăescu, Paul Ștefan Popescu, Marian Cristian Mihăescu · IFIP advances in information and communication technology · 2025
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Bowen Zhang, Shengan Zheng, Liangxu Nie et al. · 2024
Byte-addressable persistent memory (PM) has been widely studied in the past few years. Recently, the emerging eADR technology further incorporates CPU cache into the persistence domain. The persistent CPU cache is promising to optimize the write performance of PM-based storage systems and facilitate the design of concurrent crash-consistent data structures. In this paper, we propose Spash, a highly scalable persistent hash index for PM systems with persistent CPU cache. Spash fully exploits the benefits of persistent CPU cache to implement a durable linearizable index with low PM access overhead and high concurrency. Spash employs a fine-grained extendible hash architecture and a metadata-free segment design to minimize the number of PM accesses. Moreover, Spash adopts adaptive in-place updates and compacted-flush insertions, which dramatically conserve scarce PM write bandwidth by absorbing a large amount of PM write in the persistent CPU cache. Furthermore, Spash proposes a two-phase concurrency protocol and a collaborative staged doubling mechanism, which leverage the persistent CPU cache and hardware transactional memory to achieve lock-free concurrency and durable linearizability. Spash outperforms the other state-of-the-art persistent hash indexes in YCSB workloads by up to 19.6×.
Cited by 2
Kenneth William Batcher · OhioLink ETD Center (Ohio Library and Information Network) · 2008
Cited by 0Open access
Prof Dr, Martin L. Kersten, Dr. Peter et al. · 2005
Information Access, a subdivision of the research cluster Information Systems. This thesis is ready to be marked. Date: Author’s signature: This thesis is ready to be verified by the second reader. Date: Supervisor’s signature: Data-intensive query processing tasks like data mining, scientific data analysis, and decision support can leave a database system severely I/O-bound, even when common RAID configurations are used. Traditionally, this problem has been tackled by adding more and more disks, connected through expensive interconnect networks. This brute-force approach results in systems of which the price is dominated by the cost of their disk subsystems and a lot of disk space is wasted as disks are only added to gain bandwidth. A more subtle and cost-effective solution can be found in data compression, which has the potential to alleviate the I/O bottleneck. However, traditional algorithms like Huffman coding, Arithmetic coding and Lempel-Ziv style dictionary methods are not suited for this goal due to high processing overheads. In
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Bilal A. Shehada, Ahmed M. Serdah, Aiman A. Abu Samra · International Journal of Modern Education and Computer Science · 2013
Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power so power and energy consumption parameters have become one of the most important design constraint. It is one of the most attractive targets for power reduction. This paper presents an approach to enhance the dynamic power consumption of CPU cache using inverted cache architecture. Our assumption tries to reduce dynamic write power dissipation based on number of ones and zeros in the in-coming cache block data using bit to indicate is the block is mostly one or zero. This architecture reduces the dynamic write power by 17 %. We use Proteus Simulator to test that proposed circuit and performed the experiments on a modified version of the cacti6.0 simulator.
Cited by 2
Comp S · 1994
• Cache is fast memory placed between the CPU and main memory – 1 to a few cycles access time compared to RAM access time of tens – hundreds of cycles • Holds recently used data or instructions to save memory accesses. • Matches slow RAM access time to CPU speed if high hit rate • ( 90 %) • Is hardware maintained and (mostly) transparent to software • Sizes range from few kB to several MB. • Usually a hierarchy of caches (2–5 levels), on- and off-chip.
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