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About 1,957 papers for “Cache coherence”

Cache Coherence

Guy L. Steele, Xiaowei Shen, Josep Torrellas et al. · 2011

Cited by 0

No cache-coherence

Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen et al. · 2009

Consistent with the trend towards the use of many cores in SOC and 3D Chip techniques, this paper proposes a "single-cycle ring" interconnection (SC_Ring) with ultra-low latency and minimal complexity. The proposed SC_Ring allows multiple single-cycle transactions in parallel. The main features of the circuit-switched design include a set of 3-ported circuit-switched routers (4~16) and a performance/timing effective arbiter. The arbiter, called "BTPC", features single-cycle arbitration and routing-control by means of the novel Binary-Tree paths convergence and path-prediction mechanisms, to provide a highly reduced time complexity. By combining this with the integration of 3D chips, the proposed ring-based interconnection offers several advantages for hierarchical clustering in future many-core systems, in terms of cost, latency, and power reductions. Moreover, based on the proposed SC_Ring, this work realizes a "level-1 non-uniform cache architecture" (L1-NUCA) for fast data communication without cache-coherency in facilitating multithreading/multi-core as a case study. Finally, experimental results show that our approach yields promising performance.

Cited by 9

Library Cache Coherence

Keun Sup Shim, Myong Hyon Cho, Mieszko Lis et al. · DSpace@MIT (Massachusetts Institute of Technology) · 2011

Abstract—Directory-based cache coherence is a popular mechanism for chip multiprocessors and multicores. The directory protocol, however, requires multicast for inval-idation messages and the collection of acknowledgement messages, which can be expensive in terms of latency and network traffic. Furthermore, the size of the directory increases with the number of cores. We present Library Cache Coherence (LCC), which requires neither broad-cast/multicast for invalidations nor waiting for invalidation acknowledgements. A library is a set of timestamps that are used to auto-invalidate shared cache lines, and delay writes on the lines until all shared copies expire. The size of library is independent of the number of cores. By removing the complex invalidation process of directory-based cache coherence protocols, LCC generates fewer network messages. At the same time, LCC also allows reads on a cache block to take place while a write to the block is being delayed, without breaking sequential consistency. As a result, LCC has 1.85X less average memory latency than a MESI directory-based protocol on our set of benchmarks, even with a simple timestamp choosing algorithm; moreover, our experimental results on LCC with an ideal timestamp scheme (though not implementable) show the potential of further improvement for LCC with more sophisticated timestamp schemes. I.

Cited by 8Open access

Deconstructing Cache Coherence

Laverna J. Thurston · Bulletin of Miscellaneous Information (Royal Gardens Kew) · 2014

Deconstructing Cache Coherence Using Delf Laverna J. Thurston Abstract The improvement of journaling file systems has studied redundancy, and current trends suggest that the development of e-commerce will soon emerge. In fact, few biologists would disagree with the deployment of expert systems. In this paper, we concentrate our efforts on validating that e-business and XML can interfere to fix this obstacle.

Cited by 0

Exploiting Cache Affinity in Software Cache Coherence

Ms A, Hui Li, Hui Li et al. · 1994

Cache affinity is important to the performance of scalable shared memory multiprocessors. For multiprocessors without hardware cache coherence support, software cache coherence is the only alternative. Most existing software cache schemes ignore cache affinity across parallel loops. In this paper, we propose a new scheme, Cache Affinitybased Software cache coherence scheme (CAS), that exploits cache affinity across parallel loops to achieve high cache hit ratios without requiring extra hardware support. The experimental results show that the new scheme outperforms other existing schemes. 1 Introduction Private caches are widely used in scalable shared memory multiprocessors for reducing memory access latency. Multiple copies of data in caches introduce a coherence problem. Directory based hardware cache coherence schemes [26] have been used in many multiprocessor systems, such as the KSR-1 [18], Dash [20], and Alewife [1]. They provide the user a coherent memory model, but requ...

Cited by 0

Hardware Cache Coherence Protocol

Mehammed Daoui, Mustapha Lalam, B. Djamah et al. · International Journal of Computers and Applications · 2004

This article describes a new hardware cache coherence protocol based on sequential consistency. The protocol uses the directory scheme and invalidation strategy. Two circuits ensure the management ...

Cited by 0

Variable granularity cache coherence

Lily Mummert, Mahadev Satyanarayanan · ACM SIGOPS Operating Systems Review · 1994

Weak connectivity is characterized by slow or intermittent networks. Distributed file systems using weak connections must function in spite of limited bandwidth and frequent connectivity changes. Callback-based cache coherence schemes were designed to minimize client-server communication, but with an underlying assumption that the network is fast and reliable (i.e., a LAN). This paper large presents granularity callbacks as a way to reduce the client-server communication necessary to maintain file cache coherence. Large granularity callbacks trade off precision of invalidation for speed of validation after connectivity changes.

Cited by 12

Scalably Verifiable Cache Coherence

Meng Zhang · DukeSpace (Duke University) · 2013

<p>The correctness of a cache coherence protocol is crucial to the system since a subtle bug in the protocol may lead to disastrous consequences. However, the verification of a cache coherence protocol is never an easy task due to the complexity of the protocol. Moreover, as more and more cores are compressed into a single chip, there is an urge for the cache coherence protocol to have higher performance, lower power consumption, and less storage overhead. People perform various optimizations to meet these goals, which unfortunately, further exacerbate the verification problem. The current situation is that there are no efficient and universal methods for verifying a realistic cache coherence protocol for a many-core system. </p><p>We, as architects, believe that we can alleviate the verification problem by changing the traditional design paradigm. We suggest taking verifiability as a first-class design constraint, just as we do with other traditional metrics, such as performance, power consumption, and area overhead. To do this, we need to incorporate verification effort in the early design stage of a cache coherence protocol and make wise design decisions regarding the verifiability. Such a protocol will be amenable to verification and easier to be verified in a later stage. Specifically, we propose two methods in this thesis for designing scalably verifiable cache coherence protocols. </p><p>The first method is Fractal Coherence, targeting verifiable hierarchical protocols. Fractal Coherence leverages the fractal idea to design a cache coherence protocol. The self-similarity of the fractal enables the inductive verification of the protocol. Such a verification process is independent of the number of nodes and thus is scalable. We also design example protocols to show that Fractal Coherence protocols can attain comparable performance compared to a traditional snooping or directory protocol. </p><p>As a system scales hierarchically, Fractal Coherence can perfectly solve the verification problem of the implemented cache coherence protocol. However, Fractal Coherence cannot help if the system scales horizontally. Therefore, we propose the second method, PVCoherence, targeting verifiable flat protocols. PVCoherence is based on parametric verification, a widely used method for verifying the coherence of a flat protocol with infinite number of nodes. PVCoherence captures the fundamental requirements and limitations of parametric verification and proposes a set of guidelines for designing cache coherence protocols that are compatible with parametric verification. As long as designers follow these guidelines, their protocols can be easily verified. </p><p>We further show that Fractal Coherence and PVCoherence can also facilitate the verification of memory consistency, another extremely challenging problem. One piece of previous work proves that the verification of memory consistency can be decomposed into three steps. The most complex and non-scalable step is the verification of the cache coherence protocol. If we design the protocol following the design methodology of Fractal Coherence or PVCoherence, we can easily verify the cache coherence protocol and overcome the biggest obstacle in the verification of memory consistency. </p><p>As system expands and cache coherence protocols get more complex, the verification problem of the protocol becomes more prominent. We believe it is time to reconsider the traditional design flow in which verification is totally separated from the design stage. We show that by incorporating the verifiability in the early design stage and designing protocols to be scalably verifiable in the first place, we can greatly reduce the burden of verification. Meanwhile, we perform various experiments and show that we do not lose benefits in performance as well as in other metrics when we obtain the correctness guarantee.</p>

Cited by 0

Adaptive cache coherence protocols

Shen, Xiaowei, 1966- · DSpace@MIT (Massachusetts Institute of Technology) · 2000

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.

Cited by 0Open access

Classifying Cache Coherence Solutions

I. Tartalja, Veljko Milutinović · 1997

The authors propose a classification for software solutions to cache coherence in shared-memory multiprocessors and show how it can be applied to more completely understand existing approaches and explore possible alternatives.

Cited by 0

Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

Jennifer Brana, Brian C. Schwedock, Yatin A. Manerkar et al. · IEEE Computer Architecture Letters · 2023

The ever-increasing cost of data movement in computer systems is driving a new era of data-centric computing. One of the most common data-centric paradigms is near-data computing (NDC), where accelerators are placed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inside</i> the memory hierarchy to avoid the costly transfer of data to the core. NDC systems show immense potential to improve performance and energy efficiency. Unfortunately, adding accelerators into the memory hierarchy incurs significant complexity for system integration because accelerators often require cache-coherent access to memory. The complex coherence protocols required to handle both cores and cache-attached accelerators result in significantly higher verification costs as well as an increase in directory state and on-chip network traffic. Furthermore, these mechanisms can cause cache pollution and worsen baseline processor performance. To simplify the integration of cache-attached accelerators, we present Kobold, a new coherence protocol and implementation which restricts the added complexity of an accelerator to its local tile. Kobold introduces a new directory structure within the L2 cache to track the accelerator's private cache and maintain coherence between the core and accelerator. A minor modification to the LLC protocol also enables accelerators to improve performance by bypassing the local L2. We verified Kobold's stable-state coherence protocols using the Murphi model checker and estimated area overhead using Cacti 7. Kobold simplifies integration of cache-attached accelerators, adds only 0.09% area over the baseline caches, and provides clear performance advantages versus naïve extensions of existing directory coherence protocols.

Cited by 1

A Case for Cache Coherence

Ike Antkare · 2009

Recent advances in robust modalities and dis-tributed epistemologies have paved the way for 802.11 mesh networks. In fact, few ex-perts would disagree with the refinement of voice-over-IP, which embodies the natural principles of cryptography. We describe a framework for “smart ” configurations, which we call Poundal. 1

Cited by 0

Dynamic Verification of Cache Coherence

Jason F. Cantin, Mikko H. Lipasti, James E. Smith · 2007

Proposed is a method for improving the fault tolerance of cache coherent multiprocessors. By dynamically verifying coherence operations in hardware, errors caused by manufacturing faults, soft errors, and design mistakes can be detected. Analogous to the DIVA concept for single-processor systems, a simple version of the protocol functions as a checker for the aggressive implementation. An example implementation is shown, and the overhead is estimated for a small SMP system. This is work in progress, and detailed simulation results are not yet available.

Cited by 0

Exploring Cache Coherence and IPv7

Yves De Cornulier, Romain Tessera · 2009

SCSI disks and checksums, while unproven in theory, have not until recently been considered robust. Given the current status of compact in-formation, hackers worldwide shockingly de-sire the exploration of expert systems. We present new embedded modalities, which we call SobFinns. 1

Cited by 0