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About 2,168 papers for “Datapath”

Datapath

Datapath Ltd · Computer-Aided Design · 1988

Cited by 0

A Datapath Synthesis System for the Reconfigurable Datapath Architecture

2008

Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto the rDPA without manual interaction. The required algorithms of this synthesis system are described in detail. Optimization techniques like loop folding or loop unrolling are sketched. The rDPA is scalable to arbitrarily large arrays and reconfigurable to be adaptable to the computational problem. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The rDPA can be used as a reconfigurable ALU for bus oriented systems as well as for rapid prototyping of high speed datapaths. I.

Cited by 0

A datapath synthesis system for the reconfigurable datapath architecture

Reiner W. Hartenstein, Rainer Kress · 1995

A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto the rDPA without manual interaction. The required algorithms of this synthesis system are described in detail. Optimization techniques like loop folding or loop unrolling are sketched. The rDPA is scalable to arbitrarily large arrays and reconfigurable to be adaptable to the computational problem. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The rDPA can be used as a reconfigurable ALU for bus oriented systems as well as for rapid prototyping of high speed datapaths.

Cited by 86

in Approximate Datapath

R. Nowosielski, J. Hartig, G. Payá-vayá et al. · 2016

Designing VLSI circuits for high temperature applications requires the use of specialized ASIC technologies suited for operation above 250◦C. The technologies available today expose computation performance as well as the integration density far beyond state-of-the-art VLSI technologies. Especially at high temperatures, the switching speed of integrated circuits becomes very slow. Thus, the design space for implementation of digital architectures for signal processing at high temperature is restricted. This paper presents, new in context of high temperature ASIC design, and evaluates different adder architectures used in approximate computing and stochastic arithmetic. The goal is to analyze the error characteristics of these adders under out-of-specification operation like high temperature and frequency overscaling. Using these results, the best adder architecture for out-of-specification operation for a given application can be identified. The presented work describes the first step of a two-fold evaluation process, recording results from gate level simulation as well as introducing the chip design for real world experiments approved for fabrication.

Cited by 0

ABSTRACT Control Datapath

Gagan Raj, Gupta Madhur, Gupta Preeti et al. · 2008

high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design goes through both the datapath and the control logic; yet 7NextState most scheduling algorithms account only for datapath and, and output logic ignore control delay, leading to timing uncertainties in the Conlrol resulting designs. We present an estimation technique for Signals computing a fast, robust, scalable, and reasonably accurate approximation of the control delay from behavioral specifi- Status Signals ReEl cations. The delay estimate is formulated in terms of the properties of the input specification and other inputs to the synthesis process such as resource constraints.

Cited by 0

Imprecise Datapath Design

Kan Shi, David Boland, George A. Constantinides · ACM Transactions on Reconfigurable Technology and Systems · 2015

In this article, we describe an alternative circuit design methodology when considering trade-offs between accuracy, performance, and silicon area. We compare two different approaches that could trade accuracy for performance. One is the traditional approach where the precision used in the datapath is limited to meet a target latency. The other is a proposed new approach which simply allows the datapath to operate without timing closure. We demonstrate analytically and experimentally that on average our approach obtains either smaller errors or equivalent faster operating frequencies in comparison to the traditional approach. This is because the worst case caused by timing violations only happens rarely, while precision loss results in errors to most data. We also show that for basic arithmetic operations such as addition, applying our approach to the simple building block of ripple carry adders can achieve better accuracy or performance than using faster adder designs to achieve similar latency.

Cited by 1

Datapath sequential logic

William J. Dally, Ralf-Christian Härting, Tor M. Aamodt · Cambridge University Press eBooks · 2015

This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze and design digital systems. Going beyond the design of simple combinational and sequential modules, it shows how such modules are used to build complete systems, reflecting real-world digital design. All the essential topics are covered, including design and analysis of combinational and sequential modules, as well as system timing and synchronization. It also teaches how to write VHDL-2008 HDL in a productive and maintainable style that enables CAD tools to do much of the tedious work. A complete introduction to digital design is given through clear explanations, extensive examples and online VHDL files. The teaching package is completed with lecture slides, labs and a solutions manual for instructors. Assuming no previous digital knowledge, this textbook is ideal for undergraduate digital design courses that will prepare students for modern digital practice.

Cited by 0

Datapath architecture simulation

V Venkatesh Kannan, Ljam Lou Somers, Marc Voorhoeve · TU/e Research Portal · 2009

Research carried out in the context of the Octopus project under the responsibility of the Embedded Systems Institute. This project is partially supported by the Netherlands Ministry of Economic Affairs under the Senter TS program.

Cited by 0

Datapath optimization using feedback

D.W. Knapp · 2002

Describes recent experience with Fasolt, a software tool that automatically optimizes a register-level datapath. Fasolt uses a model of layout to drive the choice of optimizing transformations at the levels of scheduling and allocation; hence it is a feedback-driven optimization system. In choosing transformations, Fasolt takes placement and wiring into account in a way that has not been demonstrated in any other high-level synthesis system. Fasolt is also cyclic in that high-level transformations trigger changes at lower levels, which after analysis trigger further high-level changes. This implementation of Fasolt has an expanded set of transformation rules, timing-driven and area-driven transformations, and improved layout modeling capability. The authors present experimental results on three basic test cases and two major variations on the layout software.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 8

Technical report - Unblocking datapath

Simone Pernice, Ahmad Tarraf, Barbara Cantalupo et al. · Zenodo (CERN European Organization for Nuclear Research) · 2026

Additional descriptions of important concepts can be found in the article titled Unblocking Datapath.

Cited by 0Open access

Floorplanning with datapath optimization

Abdelhakim Safir, Baher Haroun, K. Thulasiraman · 2002

This paper presents a floorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of functional units and the schedule. The tool has combined two novel approaches: 1-A placement and routing model to handle different architectural topologies (mux. and/or bus based) suitable for FPGA's. 2-An efficient formulation for the binding of register/interconnect and combined floorplanning. The complexity of the architectural and floorplanning model, and of the cost function, have led us to the use of a stochastic optimization process. The running time of the whole process indicates the viability of the method. We show through various examples how the floorplanner improves the area and critical path delay of the datapath compared to a plain floorplanner. The improvement is about 20% for the critical path delay when this objective is a stringent constraint.

Cited by 2

Technical report - Unblocking datapath

Simone Pernice, Ahmad Tarraf, Barbara Cantalupo et al. · Zenodo (CERN European Organization for Nuclear Research) · 2026

Additional descriptions of important concepts can be found in the article titled Unblocking Datapath.

Cited by 0Open access

Technical report - Unblocking datapath

Simone Pernice, Ahmad Tarraf, Barbara Cantalupo et al. · Zenodo (CERN European Organization for Nuclear Research) · 2026

Additional descriptions of important concepts can be found in the article titled Unblocking Datapath.

Cited by 0Open access