For Low Bit, Billy Cahill, Conor Heneghan · 2008
Blocking artifacts are a major degradation affecting blockbased video compression. In this paper an adaptively based filter is proposed, whereby the type of filtering to be applied is chosen based on local image characteristics. Having three modes of filtering, it allows for strong filtering in flat areas where the blocking effect is most noticeable, detail preserving filtering in highly complex regions, while allowing for the smoothing of intermediate areas without excessively blurring the image. Objective, and more notably subjective testing, show the effectiveness of the proposed postprocessing technique. PSNR improvements of the order of 0.3 dB are found compared to the non-postprocessed image. Computational demands (less than a million operations per QCIF frame) make the proposed method practical for real time implementation.
Cited by 0
Andrey Norkin · 2022
The AV1 deblocking filter did not sufficiently attenuate visual quality artifacts when used in the AOMedia video model (AVM), especially at lower bitrates. A generalized deblocking filter described in this paper uses one equation for any filter length. The filter brings PSNR-YUV BD-rate $-\mathbf{0. 1 7 \%},\ -0.90\%,-1.07\%$, and $-0.92\%$ on All Intra, Random Access, LowDelay, and Adaptive Streaming configurations in the AOMedia common test conditions. Improvement of visual quality is observed on a number of sequences, while the computational complexity is close to that of the AVM deblocking.
Cited by 2
Andrey Norkin, Gisle Bjøntegaard, A. Fuldseth et al. · IEEE Transactions on Circuits and Systems for Video Technology · 2013
This is a correction to the “HEVC deblocking filter” article published in IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 12, Dec. 2012.
Cited by 0Open access
Yu-wen Huang, To-wei Chen, Bing-yu Hsieh et al. · 2013
This paper,presents an efficient VLSI architecture for the dehlocking filter in H.ZWIVT/AVC. We use an array of 8x4 &bit shift registers with reconligurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 pm technology. the synthesized logic gate count is only 19.1 K (not including a 96x32 SRAM and a 64x32 SRAM) when the maximum frequency is 1M) MHz. Our architecture design can easily support real-time deblocking of 720p (1280x720) 30Hz video. It is valuable for platfom-based design of H.264 codec.
Cited by 0
Li Hui · 2005
This paper describes a fast implement architecture of deblocking filter for H.264/AVC video coding, introduces the filter principles and the storage for the data. The filter can implement edge filter fast and improve the video quality.
Cited by 0
Chung-ming Chen, Chung-ho Chen · 2005
In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called “Pipeline Buffer Shift Register (PBSR). ” As a result, the performance of PBSR is 22.5 % faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37 % and 75 % respectively compared to the basic and advanced architectures of the previous proposals.
Cited by 0
P Lakshmi Amruthavalli, N. Purnachand · 2023
This paper overviews the working of in-loop deblocking filter applied in the imminent Versatile Video Coding (VVC) standard to minimize the blocking artifacts that appears at the coded block boundaries and reduces them by applying suitable filter. Compared to the former video coding standards namely HEVC and AVC, the deblocking filter provides several enhancements like lower computational complexity, significant reduction of blocking artifacts and increased parallel processing capability.
Cited by 1
Bin Sheng, Wen Gao, Di Wu · 2008
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, we propose an efficient processing order for the deblocking filter, and present the VLSI architecture according to the order. Making good use of data dependence between neighboring 4x4 blocks, our design reduces the requirement of on-chip SRAM bandwidth and increases the throughput of the filter processing. The architecture has been described in Verilog HDL, simulated with VCS and synthesized using 0.25µm CMOS cells library by Synopsys Design Compiler. The circuit costs about 24k logic gates (not including a 32x64 SRAM and two 32x96 SRAMs) when the working frequency is set to 100MHz. This design can support real-time deblocking of HDTV (1280x720, 60fps) H.264/AVC video. This architecture is valuable for the hardware design of H.264/AVC CODEC. 1.
Cited by 0
Gulistan Raja, M.J. Mirza · 2010
This paper describes a reduced complexity deblocking filter for H.264/AVC video. The proposed method modifies the selection criterion for using strong and normal filter of H.264/AVC deblocking filter. Thresholds have been set for categorization of different CIF video sequences into low, moderate, and high motion sequences using absolute sum of motion vectors. Simulation results of various low to moderate activity CIF sequences show significant reduction in computational complexity without any visible change in perceptual quality in comparison to H.264/AVC deblocking filter.
Cited by 0
Ting Liu, Chunchun Chen, Eryan Yang · 2011
In this paper, an accelerated post deblocking filter algorithm based on CUDA (Computer unifiled device architecture) technology is proposed. The algorithm is used to remove block artifacts and improves the visual quality. It is computationally intensive and usually requires high speed processors to run in real time. A commonly efficient way can be obtained using the DSP (Digital Signal Processing) or other hardware resources. Here, we put forward a software solution method. Using NVIDIA's CUDA technology, we save more hardware resources and make up the low programmability of hardware. CUDA technology assists GPU (Graphics Processing Unit) to work for CPU for large computation. In the experiment, a frame was picked up from JM (Joint Model) decoder stream and filtered by the improved algorithm. Without changing subjective quality, the result shows that the processing time saved 5.69 times than CPU.
Cited by 0
Jungyoup Yang, Kwanghyun Won, Byeungwoo Jeon · 2011
In this paper, an improved deblocking filter for intra blocks is proposed. By applying different strength of deblocking filter adaptively to intra blocks based on intra prediction mode, the proposed method not only improves visual quality but also achieves coding performance.
Cited by 0
Kausik Maiti, Sirish Kumar Pasupuleti, Raj Narayana Gadde et al. · 2016
As world is moving towards Ultra High Definition (UHD) content and display technology, high quality visual content is becoming a necessity. Deblocking filter is one of the tools used in today's video coding standards to enhance the quality of compressed video. Deblocking consumes significant percentage (~20%-33%) of total decoding cycles. Therefore, many decoder implementations tend to offload deblocking operation to additional hardware IP block or GPU to achieve real-time performance. However, hardware IP increases die area and lacks flexibility; on other hand GPUs are power hungry. In this paper, we present a reconfigurable processor based software solution along with a deblocking specific intrinsic catering to wide range of video coding standards for handling this performance bottleneck. Our experimental results show, proposed approach improves deblocking performance by a factor greater than 10 and results in processing time in the order of 140 ms for 4K UHD HEVC (60 fps, 30 mbps) stream.
Cited by 3
Zhang Chan, Jian Shuyun, Fan Liang · 2008
Block-based discrete cosine transform is widely used in many video coding standards includes H.264. Due to the property of the discrete cosine transform, it usually introduces annoying blockiness artifacts in the reconstructed video. H.264 uses an adaptive in-loop deblocking filter to reduce the blockiness artifacts. This paper introduces an algorithm for the deblocking filter in H.264. The proposed algorithm improves the filterpsilas ability in distinguishing between true edges and artificial one with the help of macroblock modes and intra prediction modes, which are readily accessible by both encoder and decoder. Experimental results shows that the proposed algorithm is able to improve both the subjective and objective quality.
Cited by 0
P. Saravanan, B. Syndia Priyadarshini, P. Vignesh Kanna et al. · 2021
Advanced Video Coding (AVC) also known as H.264 is a popular video coding standard which is used in many image processing applications. In order to fulfill the increasing demand for better video quality with less complex designs, High Efficiency Video Coding (HEVC) also known as H.265 came into picture. HEVC provides better quality with half the bit rate required for processing in comparison with AVC. In case of AVC, the design of deblocking filter is more complex due to the filtering decisions, whereas HEVC is less complex and also supports parallel processing. As there is a need for high throughput and less complex deblocking filter, a novel dual standard deblocking filter is proposed in this work which supports both AVC and HEVC. In particular, a novel filtering order which enables four edges to be processed simultaneously has been proposed for both AVC and HEVC. For AVC, the proposed design takes 18 clock cycles to process a 16 × 16 macroblock and for HEVC standard, the proposed design takes 12 clock cycles to process a 16 × 16 coding transform unit (CTU). In addition to this, the proposed design supports parallel processing concept in HEVC. The proposed design is synthesized using Xilinx ISE 14.7 and is mapped to xc5vlx30-1ff324 Virtex-5 Field programmable gate array (FPGA). Thus it helps in increasing the execution speed of the design and it is also noted that there is a reduction in number of clock cycles needed for processing when compared with the existing architectures. The physical implementation of the proposed architecture is also carried out using Semiconductor Lab (SCL) 180 nm process node.
Cited by 3
Gulistan Raja · The Nucleus · 2012
The latest video coding standard, H.264/AVC uses in-loop deblocking filter for suppression of blocking artifacts at low bit rates. The deblocking filter can effectively suppress the blocking artifacts due to low bit rate video coding, however it is highly computationally complex. This paper describes statistical analysis of H.264/AVC deblocking filter for various QCIF sequences. The deblocking filtering phenomenon can be divided into two steps: decision to apply filter (no filter/strong filter/normal filter) and application of filter. Number of operations: additions, shifts and comparisons spent in deblocking filter are measured. Moreover, frequency of usage of strong and normal filter for various video sequences is computed. It has been found that 88.49% of average number of operations is spent to take decision about type of filter (no filter/normal filter/strong filter) whereas11.51% of average number of operations is spent for filtering of samples for various QCIF video sequences.
Cited by 0Open access
Chih-Chung Fang, I‐Wen Chen, Tian‐Sheuan Chang · 2015
This paper presents a hardware-efficient deblocking filter architecture for High Efficiency Video Coding (HEVC) to reduce visual artifacts at block boundaries. This design proposes an interleaved scheduling to reduce the intermediate data storage to be 1536 bits instead of whole 8192 bits. The implementation with 90 nm CMOS technology can support real-time deblocking operation of 7682×4320@30 fps under 141.5 MHz with only 31K gate count.
Cited by 9
Teresa Cervero, A. Otero, Sebastián López et al. · Journal of Real-Time Image Processing · 2013
Cited by 4
C. Karthikeyan, Rangachar · 2013
A new international standards H.264 is used for the compression of video images, the blocking artifacts is one of the artifacts in video and image compression coding. This artifact will reduce the picture quality of the reconstructed images and video. To improve the quality of the received picture Deblocking filters are used to remove the artifacts. There are several algorithms have been proposed by researchers, this paper will introduce a Deblocking algorithm to remove the artifacts. This paper also proposes the hardware implementation for same algorithm. To reduce the power consumption of hardware implementation a technique clock gating is introduced. We achieved the result of 30% power reduction for clock gating technique at the cost of 2.3 % hardware and 5.8% clock speed.
Cited by 1
Alaa F. Eldeken, Richard M. Dansereau, Mohamed M. Fouad et al. · 2015
In this paper, a new parallel scheme for the deblocking filter (DF) in high efficiency video coding (HEVC) is proposed. This scheme is based on a parallel-straight processing order that improves the performance of HEVC DF. One of the challenges in HEVC is coding time due to computational complexity. Deblocking in HEVC is responsible for nearly 15% of the time consumed while performing video compression. As such, a parallel-straight processing order is introduced that allows improved concurrency for deblocking multiple horizontal and vertical edges. For our examined 4-core case, the approach achieves full utilization of all cores with fewer number of DF steps (i.e., two edges or more) by 27% compared to recent techniques. A four-core parallel architecture is also proposed. This new parallel scheme is implemented on a graphical processing unit (GPU) rather than a CPU to further speed up coding time. Experimental results demonstrate the ability to achieve decoded frame processing times as low as 5.0 ms for All-Intra filtering and 3.0 ms for Low-Delay filtering, corresponding to speedup factors as high as 12 and 7, respectively, compared to the HEVC reference.
Cited by 10
NTUR (臺灣機構典藏) · 2002
Cited by 0