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About 10,000 papers for “FPGA implementation”
Sergey Churayev, Bakhyt Matkarimov · 2010
We consider FPGA design flow with C/C++ to Verilog translation and verification and report on FPGA implementation of fast Fourier transform and Wiener filter for noise reduction of speech signals on Xilinx Virtex-4.
Cited by 0
Nitin Singh, Riya Sharma, Nisha Chauhan et al. · 2024
In this work, the cryptographic technique known as RSA is designed and implemented, with the goal of becoming a standard in secure communication systems. The basic idea of this algorithm is to create a confidential communication channel in between two parties (sender, and receiver). Verilog is used to code each module or block, and the Xilinx ISE_14.7 Design Suite is used to synthesize and simulate the code. A trade-off between speed, power, and space is offered, and the design is geared toward speed. FPGA is used as hardware to increase the speed and make the algorithm more secure. Our goal is to demonstrate, as a significant practical outcome, that the RSA algorithm can be implemented at secure bit lengths on a single piece of commercial hardware—FPGA and the study covers the design, optimization, and challenges of implementing RSA modules on FPGA, emphasizing modular exponentiation, key generation, and data handling.
Cited by 1
Ng , Yee Jaet · UTPedia (Universiti Teknologi Petronas) · 2009
A FPGA chip consists of thousands of programmable logic gates. This versatility allows integrated circuit designers to replicate microcontrollers or small scaled microprocessors on the board. The 68000 microprocessor is attempted to be emulated on a FPGA board. One motivation would be that this would be an alternative to the aging 68K training kit in Universiti Teknologi PETRONAS (UTP) microprocessor lab. This development includes the emulation of Arithmetic Logic Unit, Control Unit, and other essential blocks as well as the implementation of some of the 68000 Instruction Set Architecture into the FPGA core. For this project simplified processor is developed and a working prototype is completed.
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Roger Woods, John McAllister, Ying Yi et al. · 2017
As power consumption is directly related to increased temperature, improved FPGA implementations have immediate benefits for the design of the power supply to the complete system; this can result in cheaper systems and fewer components, giving a reduction in PCB area and a reduction in thermal management costs. This chapter looks at the various sources of power and introduces the concepts of static and dynamic power consumption. Then, it outlines some of the approaches applied by FPGA vendors in reducing power consumption. Generally speaking, power reduction techniques either act to minimize the switched capacitance or employ techniques to increase performance by reducing the supply voltage, thereby achieving a squared reduction in power at the expense of a linear increase in area, i.e. CL or frequency, f. The rest of the chapter is dedicated to two core topics, namely, dynamic voltage scaling and switched capacitance.
Cited by 0
Šulc, Tomáš · Brno University of Technology Digital Library (Brno University of Technology) · 2012
Předkládaná práce se zabývá architekturou 8bitového mikropočítače Sinclair ZX Spectrum 48K a její úpravou pro implementaci do obvodu FPGA. Teoretická část práce je zaměřena na popis architektury počítače ZX Spectrum rozložené do funkčních bloků s důrazem kladeným na tok signálů po sběrnicích. V praktické části práce jsou funkční bloky upraveny tak, aby při komunikaci s procesorem respektovaly původní datový tok po sběrnicích a současně využívaly dostupná rozhraní vývojové desky s FPGA obvodem Xilinx Spartan-3, na které byl projekt v rámci ověření funkčnosti prakticky realizován.
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Shirshendu Roy · 2023
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François Gosset, François‐Xavier Standaert, Jean-Jacques Quisquater · Digital Access to Libraries (Université catholique de Louvain (UCL), l'Université de Namur (UNamur) and the Université Saint-Louis (USL-B)) · 2008
Passive RFID tags are devices with very poor computational capability. How-\never an increasing number of applications require authentication of the tag. For\nthis purpose, a simple solution is to use a challenge-response protocol. For exam-\nple, the reader can send a random challenge R and the tag responds H(R + S),\nwhere S is a secret known by the reader and H is a hash function. Then, the\nreader can check whether the tag knows S. SQUASH, introduced by Adi Shamir\nin February 2008 [1], is a new hash function designed for this task. In this ar-\nticle, we describe an FPGA implementation of this algorithm minimizing the\nresources.\nSQUASH is based on the one-way function c = m2 mod n coming from the\nRabin cryptosystem [2]. To make it secure, the binary length of n must be at\nleast 1000 bits long [8]. In [1], the author suggests using a 64-bit non-linear\nfeedback shift register to generate m, a not yet factorized Mersenne's number\n(2x - 1) as modulus n, and to send out the bits of c without storing them.\nThis process avoids storing three 1000-bit long numbers. The multiplications are\nachieved by on-the-\ny convolutions, sending each bit as soon as it is computed.\nConsequently, the only needed memory aims at storing the carry of the previous\nsteps in the convolution. For the output, a window of 32 or 64 (or more) bits\nin c is used. It yields a hash function with inputs of 64 bits that is scalable in\noutput.\nIn this paper, we propose implementations designed in order to minimize the\nresources, possibly at the cost of an increased execution time. The target device\nis a Xilinx Virtex-4 XC4VLX200-10 FPGA. The algorithm recommended by Adi\nShamir has 64 bits in input and 32 in output, and n = 21277 - 1. To reduce\nthe hardware cost, we minimized the number of registers in the implementation\ndata and control part. On the XC4VLX200, the design results require 377 slices.\nThe full execution time to produce 32 bits is 63,250 clock cycles at 222 MHz,\nso we reach a throughput of 112,300 bits per second. We also implemented the\nalgorithm with other size numbers. For 128 bits in input and 64 in output, we\nget 619 slices and 104,114 clock cycles at 206 MHz. In general, the length of the\noutput in\nuences the execution time while the length of the input in\nuences the\nnumber of registers and slices.
Cited by 16Open access
Mutina, Petr · Brno University of Technology Digital Library (Brno University of Technology) · 2020
The main goal of this work was to design simplified version of Stack game in VHDL language and implementation to FPGA development kit Spartan-3. There is standard computer keyboard connected via PS/2 interface as input and monitor with VGA interface as output. It was necessary to design 21bit VGA convertor for this project.
Cited by 0Open access
Steven M. Parmley, Steven M. Parmley, Steven M. Parmley et al. · 1997
Cited by 0
Hema Manjule, Savitha S. Upadhya, Nilashree Wankhede et al. · 2020 International Conference for Emerging Technology (INCET) · 2020
In the existing Medical Linear Accelerator (LINAC) systems with Field Programmable Gate Array (FPGA) based control console, most of the subsystems of the LINAC were controlled and monitored using serial communication methods like RS-232, RS-422 or RS-485. Now a days, most of the subsystems or controllers used in the LINAC system support Ethernet communication which has not been implemented in the system as yet. The traditional serial communication methods as mentioned above also have a limitation of data transfer speed. Therefore this paper involves solutions to these two observed problems. Ethernet is a standard way to connect computers on a network over a wired connection. Hence, the objective of this paper is to implement Ethernet based Transmission Control Protocol/Internet Protocol (TCP/IP) on FPGA based control console for high speed communication with many subsystems of the LINAC system connected using unshielded twisted pair wiring. Thus, this paper will facilitate interoperability between various subsystems of the LINAC connected using the Ethernet protocol. This system is designed in ARTY-7 FPGA and has been implemented using VHDL language.
Cited by 4
Jean-jacques Quisquater · 2016
Passive RFID tags are devices with very poor computational capability. How-ever an increasing number of applications require authentication of the tag. For this purpose, a simple solution is to use a challenge-response protocol. For exam-ple, the reader can send a random challenge R and the tag responds H(R ⊕ S), where S is a secret known by the reader and H is a hash function. Then, the reader can check whether the tag knows S. SQUASH, introduced by Adi Shamir in February 2008 [1], is a new hash function designed for this task. In this ar-ticle, we describe an FPGA implementation of this algorithm minimizing the resources. SQUASH is based on the one-way function c = m2 mod n coming from the Rabin cryptosystem [2]. To make it secure, the binary length of n must be at least 1000 bits long [8]. In [1], the author suggests using a 64-bit non-linear feedback shift register to generate m, a not yet factorized Mersenne’s number (2x − 1) as modulus n, and to send out the bits of c without storing them.
Cited by 0
Horák, Martin · Brno University of Technology Digital Library (Brno University of Technology) · 2008
Diplomová práce je zamena na implementaci OFDM modemu do programovatelného obvodu FPGA. Výhody vyuití OFDM jsou zejmé, vysoká spektrální úinnost a robustnost vi mnohacestnému íení. Základní principy OFDM signál jsou proto zmínny na nkolika prvních stranách. V tomto pípad byla vyuita konstrukce OFDM signálu pomocí inverzní Fourierovy transformace s vnitní modulací nosných 256-QAM pro zvýení kapacity kanálu. Jeliko je algoritmus výpotu diskrétní Fourierovy transformace pomrn sloitý, je vyuit efektivní algoritmus IFFT a jeho algoritmem vyuitým v obvodech DSP se také budeme zabývat. Dále jsou analyzovány moné problémy spojené s realizací takto zvoleného modemu a poskytnuta vhodná eení pro jejich eliminaci. Ped zapoetím implementace návrhu do vlastního obvodu je vak nutno provést nezbytné teoretické simulace v programu Matlab. Analyzovaný OFDM signál je podroben statistické i spektrální analýze. Nkolik stran je dále vnováno samotnému HW, pro který je návrh uren a dále pokrauje kapitola vnovaná simulacím v obvodovém simulátoru ModelSim. Pro vlastní programování vhdl kódu je pouito programu ISE Xilinx. V závru práce jsou pak uvedeny praktická mení potvrzující funknost daného modemu. Vechny skripty a data pouité v rámci práce jsou distribuovány na piloeném médiu.
Cited by 0
M Shilpashree, Sourabh KS, S Chetan et al. · 2021
Differential phase shift keying (DPSK) is a modulation scheme that facilitates non coherent demodulation and is employed for various applications such as Wireless Local Area Networks (WLANs), Bluetooth and RFID communication. In this paper, design, development and hardware implementation of a new demapping scheme for Differential 8-PSK (D8PSK) demodulator on a Zynq 7000 FPGA based ZED board is proposed using the concepts of model based design. The proposed work can be easily extended to other M-ary DPSK schemes.
Cited by 1
Ognyan Manchev, B. Donchev, Kostadin Pavlitov · 2004
Controlling modern systems is a difficult to implement task. The number of controlled parameters and monitored values is greatly increasing and present means of computing become unusable, inefficient or inadequately expensive. Conventional computers suffer the lack of I/O connections, speed and stability in the area of industrial applications, parameter control, optical or sound recognition. An interesting approach to solving problems concerning multiple input parameter handling and noise – resistance is processing data the way the human brain does. The brain is a highly complex, nonlinear and parallel information processing system with the capability of organizing neurons (basic processing units) such as to perform these computations on a speed, greater than the speed of the fastest algorithmic machine existing today. The neuron – a basic cell of this parallel computer comprises of receptors (dendrites), computing body (core) and synaptic connections to adjacent neurons. Synaptic connection properties define how the brain processes particular input information. The organization of these connections is referred to as knowledge. A computational system modeling the way the brain processes information is called Artificial Neural Network (ANN) and therefore its components are called artificial neurons. Artificial neurons are organized in layers. Cascaded layers form an ANN which can classify objects or perform signal processing tasks. Differences in principles of operation of conventional algorithmic computers and ANNs define fields of application for both of them. While algorithmic approach can be used to do explicitly defined tasks, such as word processing or accounting, parallel processing structures manage incompletely defined problems, concerning signal processing, sound and image recognition or shape classification. Results from a comparison between conventional computers and neural networks can be summarized in the following table:
Cited by 5
Wu, Haotian · DR-NTU (Nanyang Technological University) · 2025
With the rapid development of AI (Artificial Intelligence) technology, its application and deployment on embedded platforms has become one of the key research focuses in the industry. YOLO (You Only Look Once) is the most frequently mentioned algorithm. However, traditional CPU (Central Processing Unit) unable to meet the real-time requirements. The power consumption of high-performance GPU (Graphics Processing Unit) is not acceptable for end devices. FPGAs (Field-Programmable Gate Arrays) achieve efficient computation and memory access, made them the mainstream choice for embedded deployment. Vitis HLS (High-Level Synthesis) enables the conversion from high-level to hardware languages, greatly simplifying the development process. This dissertation takes the lightweight but highly accurate YOLOv4-tiny model as the research object and realizes efficient acceleration on the Xilinx ZYNQ-7020 platform through overlapping architectures reusable PE (Processing Element) design, as well as various optimization strategies such as ping-pong buffering, operator fusion, data reuse and quantization mechanism with HLS primitive instructions. Through hardware and software co-design and integration, we achieved a frame rate of 15.58 FPS (Frames Per Second) at a clock frequency of 150 MHz while power consumption was only 2.514 W, providing real-time processing capability and low power consumption.
Cited by 0
Hájek, Radek · Brno University of Technology Digital Library (Brno University of Technology) · 2014
Bakalářská práce se zabývá implementací jádra procesoru Atmel AVR do programovatelného hradlového pole FPGA v jazyce VHDL. Shrnuje základní architekturu procesoru a způsoby adresování v něm. V rámci práce bylo navrženo vlastní jádro procesoru včetně několika periferií tak, aby co nejvíce odpovídalo architektuře a instrukční sadě procesoru ATtiny26. Vytvořený VHDL popis byl verifikován a funkčně testován.
Cited by 0
Solar, Pavel · Brno University of Technology Digital Library (Brno University of Technology) · 2010
Diplomová práce stručně rozebírá princip OFDM modulace, možnosti synchronizace a odhadu frekvenční charakteristiky kanálu v OFDM. Je vytvořen jednoduchý model OFDM systému v programu MATLAB. Kombinací schématického popisu a popisu v jazyce VHDL je vytvořen ve vývojovém prostředí ISE behaviorální popis OFDM demodulátoru pro implementaci do FPGA.
Cited by 0
MARSI, STEFANO, SICURANZA, GIOVANNI · ArTS Archivio della ricerca di Trieste (University of Trieste https://www.units.it/) · 2001
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Zorer, Tolga · OpenMETU (Middle East Technical University) · 2019
In today’s complex technological systems, there is a need of multi tasking several units running in accordance. Each unit is composed of several intelligent microcontroller cards. Each intelligent card performs a different task that the unit is responsible of. For this reason, there is a need of common communication bus between these cards in order to accomplish the task duties. VME (Versa Module Euro-Card) bus is a well known, the most reliable and the commonly used communication bus, even if it was standardized three decades ago. In this thesis work, the world wide accepted VME parallel bus protocol is implemented on FPGA (Field programmable Gate Array). The implementation covers the VME standard slave protocols. The VME Slave Module has been developed by VHDL (Very high level Hardware Description Language). The simulations have been carried over a computer based environment. After the verification of the VHDL code, an Intellectual Property (IP) core is synthesized and loaded into the FPGA. The FPGA based printed circuit board has been designed and the IP core’s function has been tested by bus protocol checkers for all of its functionality. The designed hardware has several standard serial communication ports, such as; USB, UART and I2C. Through the developed card and the add-on units, it is also possible to communicate with these serial ports over the VME bus.
Cited by 0Open access
H D Nalina · International Journal Of Trendy Research In Engineering And Technology · 2024
Field Programmable Gate Array (FPGA) are versatile devices that can be programmed to implement various digital circuits, including communication protocols like Serial Peripheral Interface (SPI). The Serial peripheral interface protocol is a synchronous serial communication interface that allows for full duplex communication between a master device and a multiple slave MOSI, MISO, SCLK, and SS. MOSI and MISO are data lines, while SCLK is the clock signal generated by the master to synchronize transfers. SS is used by the master to select individual slave devices. By implementing the SPI protocol in FPGA, to gain flexibility and customization, as FPGAs can be reprogrammed for different applications without the need for dedicated hardware changes. The FPGA implementation of the Serial Peripheral Interface (SPI) protocol involves a structured methodology. With the help of pipeline buffer and DAM technique power dissipation is performed effectively. Finally, integrate the FPGA SPI module into the larger system, ensuring seamless communication with other components or microcontrollers. This systematic approach ensures a reliable and tailored FPGA based SPI implementation.
Cited by 0Open access