Douglas Sheldon, Tucker McClure · NASA STI Repository (National Aeronautics and Space Administration) · 2013
Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.
Cited by 0
Krátký, Michal · Brno University of Technology Digital Library (Brno University of Technology) · 2012
Cílem bakalářské práce je vytvoření laboratorní úlohy na problematiku vibrodiagnostika točivých elektrických strojů. Práce je rozdělena na teoretickou a praktickou část. V teoretické části jsou informace týkající se elektrických točivých strojů, jejich poruch a technické diagnostiky. Mezi ně patří mimo jiné vibrodiagnostika, kterou se v této práci zabývám. V praktické části je navržena laboratorní úloha na vibrodiagnostiku točivých elektrických strojů, u které je názorně ukázáno jaký vliv mají vibrace na stroj v provozu. V úloze je používán asynchronní motor 1LA7080 , vibrometr MV-5L a bezkontaktní otáčkoměrem UNI-T UT372. Druhá úloha je na diagnostiku rozběhového proudu. Zde bude analyzován rozběhový proud motoru s rotorovou nesymetrií 1LA7080 a rotorovou symetrií 1LA7090. Na těchto motorech bude ukázáno, jaký vliv mají proudové zákmity na magnetické pole motoru ve vzduchové mezeře.
Cited by 0
C. L. Chen, R. A. Rutledge · IBM Journal of Research and Development · 1984
Memory systems in modern computers employ a variety of methods to achieve fault tolerance, such as single- or double-error correction, page deallocation, or the use of spare chips or cells. Such methods ensure that the failure rate of the system is considerably less than the sum of the failure rates of the components. However, these methods also complicate the task of evaluating system reliability. The memory reliability function is too intractable to handle analytically, and we must turn to Monte Carlo methods. This paper describes the Fault-Tolerant Memory Simulator (FTMS), an interactive APL program which uses Monte Carlo simulation to evaluate the reliability of fault-tolerant memory systems.
Cited by 13
Toshirou Nishida, Shunsuke Miyamoto, Tokinori Kozawa et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987
This paper describes the algorithm, implementation, and evaluation results of a new fault simulator called RFSIM, which is designed for combinational circuits. In order to accelerate fault simulation, two basic principles are introduced, a Detectable Fault Only (DFO) principle and a Candidate Gate Once (CGO) principle. The DFO principle is a dynamic reduction algorithm, which aims at drastically reducing computational complexity by utilizing blocking gate information. The CGO principle is an implementation technique which is utilized to implement the DFO principle effectively. Experimental results show that RFSIM is more than 10 times faster than a conventional concurrent fault simulator, and confirms that the DFO principle contributes to a drastic reduction in the number of faults to be simulated. A fault reduction ratio of around 25 to 1 was achieved in one of the benchmark circuits.
Cited by 19
J. Sapiecha, Krzysztof Sapiecha, Stanisław Deniziak · 2002
In this paper a new efficient approach to bit-parallel fault simulation for sequential circuits is introduced and evaluated with the help of ISCAS89 benchmarks. Digital systems are modelled using Hierarchical Ternary Decision Diagrams (HTDDs). It leads to substantial reduction of both the number of simulated faults and calculations needed for simulation. Moreover, an approach presented in this paper is able to handle High-Level Primitives (HLPs) in addition to simple gates (GLPs), so it can be applied for hierarchical and multi-level simulation.
Cited by 1
T. J. Snethen · 1988
Article Free Access Share on Simulator-oriented fault test generator Author: T. J. Snethen IBM System Products Division -- East Fishkill, Hopewell Junction, New York IBM System Products Division -- East Fishkill, Hopewell Junction, New YorkView Profile Authors Info & Claims 25 years of DAC: Papers on Twenty-five years of electronic design automationJune 1988 Pages 342–347https://doi.org/10.1145/62882.62922Online:01 June 1988Publication History 27citation143DownloadsMetricsTotal Citations27Total Downloads143Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Cited by 29Open access
P.R. Sureshkumar, J. Jacob, M.K. Srinivas et al. · 2002
We propose several improvements to the well known deductive fault simulation algorithm. First, sensitivity analysis is used during true value simulation to classify each gate of the circuit into one of the two classes, namely, definitely sensitive (DS) or potentially sensitive (PS). For these classes, simple rules are given to compute the output fault list from the input fault lists. Further, the basic operations of set union, set intersection and set difference, used in fault list computation, are made highly efficient by novel pointer referencing on implicitly ordered fault lists. Performance enhancements over the basic deductive fault simulation algorithm are demonstrated by experimental results on ISCAS-85 combinational benchmark circuits. Experimental results on ISCAS-89 sequential benchmarks show that our improvements make the simulator faster than a highly efficient concurrent fault simulator, Hysim-3.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 3
Shyh‐Jye Jou, Shwu-Huey Chiou, Tao Yin et al. · IEE Proceedings G Circuits Devices and Systems · 1993
An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective tracc and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system.
Cited by 0
David May, Walter Stechele · 2013
The reduction of CMOS structures into the nanometer regime, as well as the high demand for low-power applications, animating to further reduce the supply voltages towards the threshold, results in an increased susceptibility of integrated circuits to soft errors. Hence, circuit reliability has become a major concern in today's VLSI design process. A new approach to further support these trends is to relax the reliability requirements of a circuit, while ensuring that the functionality of the circuit remains unaffected, or effects remain unnoticed by the user. To realize such an approach it is necessary to determine the probability of an error at the output of a circuit, given an error probability distribution at the circuits' elements. Purely software-based simulation approaches are unsuitable due to the large simulation times. Hardware-accelerated approaches exist, but lack the ability to inject errors based on probabilities, are slow or have a large area overhead. In this paper we propose a novel approach for FPGA-based, probabilistic, circuit fault simulation. The proposed system is a mainly hardware-based, which makes the simulation fast, but also keeps the hardware overhead on the FPGA low by exploiting FPGA specific features.
Cited by 4
Zhiqiang Cai, Shudong Sun, Shubin Si et al. · 2013
Machine fault diagnosis is a field of mechanical engineering concerned with finding faults arising in machines. In this paper, we use the Bayesian network (BN) classifiers and data mining technology to diagnose different kinds of rotor faults in machinery fault simulator (MFS) under varied loads. First of all, three kinds of popular BN classifiers are introduced as the diagnosis model for rotor fault, and the fault diagnosis modeling methods based on BN classifiers is established by data mining. Then, a MFS is introduced and applied to generate the vibration data of system with different rotor faults under varied loads, as dataset 1, dataset 2 and dataset 3. At last, the dataset 1 generated by MFS is used to demonstrate the rotor fault diagnosis process with BN classifiers. The same procedures are also implemented for dataset 2 and dataset 3 to show the difference of diagnosis results under varied loads.
Cited by 5
U.K. Bhattacharyya, Mohan Gurusamy, Indranil Gupta · 2005
The present paper reports the outcome of an effort to implement the concurrent fault simulation [ Ulrich 1973] algorithm on a transputer based multiprocessor. The algorithm as implemented have been run on several ISCAS benchmark circuits [Brglez 1985] and the performance with regards to speedup and efficiency evaluated.
Cited by 0
Mark J. Flomenhoft, Brenda M. Csencsits · ACM SIGDA Newsletter · 1974
A logic circuit simulator implemented on a mini-computer with 16K core handles 1000 zero- and unit-delay gates. Single "stuck-at-0", "stuck-at-1", and "short-circuit" faults are simulated in parallel seven at a time using a table-driven selective-trace fault-injection algorithm. For a typical 100-gate circuit the simulation rate for the fault-free circuit or for a group of seven faults is about 800 input patterns per minute, and a complete fault simulation run takes about 5 minutes and costs $1.This paper, aimed at simulator program-designers rather than users, describes technical details of the implementation including minicomputer considerations, the data structure, coding three-valued-logic for efficient parallel simulation, the selective-trace algorithm, the recognition and resolution of critical races in flip-flops, the recognition and resolution of circuit oscillations, implicit fault collapsing, and short-circuit fault simulation.
Cited by 5
Luana Gabriele Oliveira da Silva, Maria Sikora, Luisa Yumi Antunes Kaneko et al. · 2024
Cited by 0
David May, Walter Stechele · 2012
A recent approach to deal with the challenges that come along with the shrinking feature size of CMOS circuits is probabilistic computing. Those challenges, such as noise or process variations, result in a certain probabilistic behavior of the circuit and its gates. Probabilistic Computing, also referred to as pCMOS, does not try to avoid the occurrence of errors, but tries to determine the probability of errors at the output of the circuit, and to limit it to a value that the specific application can tolerate. Past research has shown that probabilistic computing has potential to drastically reduce the power consumption of circuits by scaling the supply voltage of gates to a value where they become non-deterministic, while tolerating a certain amount of probabilistic behavior at the output. Therefore, one main task in the design of pCMOS circuits is to determine the error probabilities at the output of the circuit, given a combination of error probabilities at the gates. In earlier work, pCMOS circuits have been characterized by memory-consuming and complex analytical calculations or by time-consuming software-based simulations. Hardware-accelerated emulators exist in large numbers, but miss the support of injecting errors with specified probabilities into as many circuit elements the user specifies at the same time. In this paper, we propose an FPGA-based fault simulator that allows for fast error probability classification, injection of errors at gate- and RT-level, and that is furthermore independent on the target architecture. Moreover, we demonstrate the usefulness of such a simulator by characterizing the probabilistic behavior of two benchmark circuits and reveal their energy-saving capability.
Cited by 12
Jer Min Jou, Shung-Chih Chen · 2002
A new combinational fault simulator, PARCRIPT, which combines the merits of the concept of the parallel fault simulation and the efficiency of the critical path tracing (CRIPT), is presented. The key idea of PARCRIPT is to simultaneously propagate the criticalities of the potential stems to determine whether a potential stem is critical. Critical path tracing then traces from the critical potential stem to find the detected faults inside the fanout-free region. Experimental results show that PARCRIPT run 2-5 times faster than PROOFS for 10 combinational benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A. K. Bose, P. Kozak, C.-Y. Lo et al. · 1988
This paper describes a fault simulator for MOS LSI circuits.
Cited by 1Open access
Zhang Bing-d · 2014
A kind of device used for simulating the process level fault of intelligent substation is designed to test the protection relay.Based on the capture-modify-forward method,the sampling value(SV) and generic object oriented substation event(GOOSE) in the process level network is transformed artificially.The information-entropy detection method is used to diagnose the voltage sags so that joint simulation between process level fault and power system fault can be realized.The fault simulator can easily access the process level network with the full duplex design.Out of consideration for both the operation time and hardware consumption,a muitiply-accumulator with less pipeline levels is developed and multiplexing technology is used in information-entropy arithmetic.Tests show that the increased transmission delay by the fault simulator is less than3 us,which won't have an effect on the process level network.
Cited by 1
Budde, Carlos E., Ruijters, Enno · Figshare · 2020
Artifact that accompanies the submission of the paper "The Dynamic Fault Tree Rare Event Simulation" to the QEST 2020 conference.<br>
Cited by 0Open access
Cioroaica, Emilia, Kuhn, Thomas · Fraunhofer-Publica (Fraunhofer-Gesellschaft) · 2016
S.641-646
Cited by 1
Chitresh Nayak, Vimal Kumar Pathak · International Journal of Recent advances in Mechanical Engineering · 2015
Recent years have seen the rise of vibration problems associated with structures, which are more delicate and intricate, machines that are faster, more complex and production process that are automated and interlinked. The occurred problems are directly related to demands of lower investment, running and maintenance cost in incidence with the requirement of increase productivity and efficiency. This work developed aMachine Fault Simulator (MFS),whichis the most comprehensive laboratory scale machine on the market for performing rotor dynamics experiments.Also, it helps in learning vibration signature of the most common machinery faults in a controlled manner without compromising your quality production/ profits. The bench top system has a spacious modular design featuring versatility, operational simplicity and robustness in depth studies of a variety of faults can be conducted using over many applications. Some examples are rolling element bearing defects, Gear defect, belt and pulley defect, motor bearing defect.
Cited by 3Open access