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About 1,176 papers for “L2 cache”

L2 Cache

SpringerReference · 2011

Cited by 0

L2 cache modeling for scientific . . .

Fengguang Song, Shirley Moore, Jack Dongarra · 2008

It is critical to provide high performance for scientific applications running on Chip Multi-Processors (CMP). A CMP architecture often comprises a shared L2 cache and lower-level storages. The shared L2 cache can reduce the number of cache misses if the data are accessed in common by several threads, but it can also lead to performance degradation due to resource contention. Sometimes running threads on all cores can cause severe contention and increase the number of cache misses greatly. To investigate how the performance of a thread varies when running it concurrently with other threads on the remaining cores, we develop an analytical model to predict the number of misses on the shared L2 cache. In particular, we apply the model to thread-parallel numerical programs. We assume that all the threads compute homogeneous tasks and share a fully associative

Cited by 0

ABSTRACT Location Cache: A Low-Power L2 Cache System

Rui Min, Wen-ben Jone, Yiming Hu · 2008

While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large setassociative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache. The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly. We used the CACTI cache model to evaluate the power consumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is powerefficient. In the simulated cache configurations, up-to 47 % of cache accessing energy and 25 % of average cache access latency can be reduced.

Cited by 0

4.2 Location Cache: A Low-Power L2 Cache System

Rui Min, Wen-ben Jone, Yiming Hu · 2013

While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large setassociative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache. The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly. We used the CACTI cache model to evaluate the power consumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is powerefficient. In the simulated cache configurations, up-to 47 % of cache accessing energy and 25 % of average cache access latency can be reduced.

Cited by 0

ORL – Modified L2 Cache Replacement Algorithm

Sean Mcnee, Staffan Strand · 2008

A limit to computer system performance is the miss penalty for fetching data and instructions from lower levels in the memory hierarchy. There are two approaches to reducing this penalty. The first approach is to reduce the miss rates of the higher cache levels by utilizing an effective replacement policy that does not replace data that is going to be needed. The second approach is to reduce the penalty of the miss by adding more cache levels to the hierarchy. Both approaches are discussed in this study. We first consider an algorithm proposed by [1] called Online Reference Locality (ORL) aimed at exploiting temporal locality in programs. We then compare this method with the standard LRU replacement policy. We also explore adding a third level of cache to the memory hierarchy to examine the performance improvements gained by reducing the miss penalties in a higher level of memory.

Cited by 0

New Prefetch Technique Design for L2 Cache

Wenxin Qu, Xiaoya Fan, Ying Hu et al. · 2006

The memory system remains a major performance bottleneck in the modern and future architectures. Cache unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (timing stride prefetching, TSP), which is suitable for prefetching at the L2 cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (instructions per cycle) is increased by 8.3%

Cited by 0

Optimization of Regressions in L2 Cache Verification

Basaweshwari, H. V. Ravish Aradhya, Robert Chan et al. · 2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA) · 2020

In a repetitive and progressive development of configurable IP core environment, Regression testing in design verification plays a vital role. As size of the design continues to grow accordingly increases the complexity of verification and regression time. However, it is a very well known fact that maintaining regression quality and reducing regression time is very difficult. In this paper, a novel technique is proposed for configurable L2 cache of IP cores, in which moving all plusargs from command line of simulation launching regression scripts into the testbench as an option groups and then randomizing the option groups during simulation for each test case. From the proposed regression optimization technique overall 42.33% machine cycles, 42.01% of CPU time is saved with coverage more or less similar as traditional one for multiple rounds of runs.

Cited by 2

Priority L2 cache design for time predictability

Jun Yan, Wei Zhang · International Journal of Embedded Systems · 2016

L2 caches are usually unified, and the possible interferences between instructions and data make it very hard, if not impossible, to perform timing analysis for unified L2 caches. This paper proposes a priority L2 cache to achieve both time predictability and high performance for real-time systems. The priority cache allows both the instruction and data streams to share the aggregate L2 cache space while preventing them from mutually replacing each other at runtime. While separate L2 caches can also achieve time predictability, our performance evaluation shows that the instruction priority cache (i.e., giving instructions priority over data) outperforms separate L2 caches. Compared to a unified L2 cache, the instruction priority cache degrades performance by only 1.1% on average. Moreover, we implement a prototype of the priority L2 cache on Virtex-6 FPGA and find hardware overhead of the priority L2 cache is very small.

Cited by 0

Characterization of Context Switch Effects on L2 Cache

Direction Of Dr. Yan Solihin, Abdulaziz Eker · 2007

Multitasking is common in most systems. In order to use the processor resources efficiently, a multitasking system schedules processes to run for certain intervals by switching (saving and restoring) their contexts. However, since processes bring their own data to the cache when they are running, context switching causes each process to suffer from more cache misses. The behavior of L2 cache misses due to context switches activities under different cache configurations, working-set sizes, and process priorities has not been sufficiently investigated. Analysis of this behavior will give insights about the reasons and ways to mitigate these misses. The first contribution of this paper is the characterization of how context switch misses at the L2 cache is affected by process priorities. The paper also characterizes the context switch effect with various cache configurations, including the size and associativity of the cache. Finally, it defines two types of misses that occur due to context switches. Replacement context switch misses occur when a process ’ working set is replaced by an interfering process. Reorder context switch misses occur due to reordering of lines by an interfering process, i.e. moving lines from more recently used to less recently used position. Through the characterization, we found that the number of context switch misses signifi-cantly increases with lower priorities. On average, on a Linux operating system, a process with the lowest priority suffers 15.4 × more L2 cache misses due to the context switch ef-fect compared to when time-sharing is not used, while the process with a relatively higher priority suffers only 1.2 × more misses. In addition, we observed that the impact of con-text switch is affected more by the priority of the process itself, rather than the priority of the interfering process. We also observed that reorder context switch misses increase with higher associativity. Finally, the context switch effect is strongest when a process ’ working set size is close to the cache size.

Cited by 0

Development of a Light Weight L2-Cache Controller

Arildsson, Måns · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2022

An L2 cache is a device that buffers data in fast memory closer to the Central Processing Unit(CPU) in order to deliver its contents with much lower latency than can otherwise be achieved bymain memory. This provides a substantial performance increase in many systems as the memoryinterface is often a bottleneck. The goal of this thesis is to develop a simple L2 cache usingVHDL for Cobham Gaisler’s open source hardware library GRLIB which currently lacks such acore. The outcome of the thesis is the IP core L2C-Lite which will be released in Febuary of 2022 as an addition to GRLIB. L2C-Lite has been integrated into multiple systems and has providedmajor performance gains in applications running under linux as well as other benchmarks. Inaddition, some potential improvements have been identified to further increase the performanceof the cache, as well as improve its usability in systems.

Cited by 0Open access

Soft Error Benchmarking for L2 Cache with PARMA

Jinho Suh, Murali Annavaram, Michel Dubois · HAL (Le Centre pour la Communication Scientifique Directe) · 2010

Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making caches more susceptible to soft errors. To counter the problem, a plethora of protection schemes are being proposed to reduce the power and area overheads of cache protection. Accurate methods to measure and compare the effectiveness of such schemes are sorely needed. This paper introduces a unified reliability benchmarking framework with PARMA (Precise Analytical Reliability Model for Architecture). PARMA is a rigorous analytical framework to measure the failure rate in the presence of soft errors under any protection scheme. PARMA continuously and accurately accounts for the increase of failure density due to soft errors affecting program behavior during an execution. We have implemented the PARMA framework on top of a cycle-accurate simulator to benchmark Level-2 cache failure rates for a set of CPU 2000 benchmarks. Three protection schemes are compared: parity, word-level 1-bit ECC and block-level 1-bit ECC. 1.

Cited by 1Open access

Efficient L2 Cache Management to Boost GPGPU Performance

Francisco Candel Margaix · 2019

In recent years, the growing need for computing capacity has become a challenge that has led the industry to look for alternative architectures to conventional out-of-order superscalar processors, with the goal of enabling an increase of computing power while achieving higher energy eciency.

Cited by 0Open access

Way-predicting L2 cache for Multi-Core Processors

Juan Fang, Mei Guo · 2011

This paper proposes a new method using way prediction based on cache partition to achieve low energy consumption and maintains high performance as more as possible. If the prediction is hit, only a single cache way accessed, instead of accessing all the ways in a set, while the prediction is miss, the core that requests the L2 access need to access the rest ways, which are assigned to it by the cache partition strategy, instead of accessing all the rest ways. Results turn out that way prediction based on cache partition L2 cache can achieve 54% Energy delay product (EDP) reduction.

Cited by 0

Performance Improvements of an Open-source L2 Cache

Roche Peris, David · RiuNet (Politechnical University of Valencia) · 2024

[CA] L’alt interés industrial en els processadors RISC-V de codi obert han generat la necessitat de nous components més complexos que puguen optimitzar al màxim les prestacions dels processadors. Les caches compartides, generalment l’L2 en processadors
\nembeguts d’altes prestacions, són un dels components més crítics en els Sistemes en un
\nChip (SoCs). No obstant això, encara que existeixen molts processadors RISC-V multinucli, les implementacions de caches L2 actuals són generalment molt més simples que les
\npresents en processadors comercials.
\nAquest projecte presenta les millores d’una cache L2 de codi obert, implementant
\noptimitzacions ben estudiades i presents en productes comercials per millorar les prestacions de la cache. Concretament, es posa enfasi en la implementació de dues millores:
\nparticionat basat en vies, i transferències no bloquejants. La cache ha sigut descrita en
\nRTL i prototipada i testejada en una FPGA. Els resultats mostren que aquesta nova cache
\nmillora signicativament les prestacions i la qualitat de servei (QoS) dels sistemes multinucli.

Cited by 0Open access

Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache

Jasmine Madonna Sabarimuthu, T. G. Venkatesh · IEEE Transactions on Computers · 2017

Reuse distance is an important metric for analytical estimation of cache miss rate. To find the miss rate of a particular cache, the reuse distance profile has to be measured for that particular level and configuration of the cache. Significant amount of simulation time and overhead can be reduced if we can find the miss rate of higher level cache like L2 cache from the RD profile with respect to a lower level cache (i.e., cache that is closer to the processor) such as L1. The objective of this paper is to give an analytical method to find the miss rate of L2 cache for various configurations from the RD profile with respect to L1 cache. We consider all three types of cache inclusion policies namely (i) Strictly Inclusive, (ii) Mutually Exclusive and (iii) Non-Inclusive Non-Exclusive policy. We first prove some general results relating the RD profile of L1 cache to that of L2 cache. We use probabilistic analysis for our derivations. We validate our model against simulations, using the multi-core simulator Sniper with the PARSEC and the SPLASH benchmark suites.

Cited by 17