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About 4,263 papers for “LDPC decoding”
Juntan Zhang, Yige Wang, Marc Fossorier et al. · 2005
Replica shuffled belief propagation decoders of low-density parity-check codes are presented. The proposed decoders converge faster than standard and shuffled belief propagation decoders. Simulations shw that the new decoders offer good performance versus complexity trade-offs.
Cited by 0
Ligter, Luca · TU/e Research Portal
Cited by 0
Zhixing Yang, Nan Jiang, Kewu Peng et al. · 2008
A high-throughput decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) codes is developed in this paper. Regular pipelined schemes of the partially parallel decoder, which are adaptable to various decoding requirements, are derived to simplify the design and implementation. Utilizing normalized uniformly most powerful (UMP) belief propagation (BP) algorithm, pipelined partially parallel decoders for (7493, 3048), (7493, 4572) and (7493, 6096) LDPC codes are implemented on FPGA. Synthesis results show that, with 30 decoding iterations, the decoders for these codes archive throughputs of 108, 172 and 237 Mbps at the maximum operating frequencies of 151, 158 and 163 MHz respectively. The proposed architecture increases decoding throughput by more than four times compared with that of the traditional decoder.
Cited by 5
S. Sharifi Tehrani, Warren J. Gross, Shie Mannor · IEEE Communications Letters · 2006
This letter presents the first successful method for iterative stochastic decoding of state-of-the-art low-density parity-check (LDPC) codes. The proposed method shows the viability of the stochastic approach for decoding LDPC codes on factor graphs. In addition, simulation results for a 200 and a 1024 length LDPC code demonstrate the near-optimal performance of this method with respect to sum-product decoding. The proposed method has a significant potential for high-throughput and/or low complexity iterative decoding.
Cited by 168
Werner Henkel, Nazia Islam, M. Ahmed Leghari · 2019
Encoding and channel convolution and the corresponding equalization and decoding are a serial concatenation. One might consider the solution to be iterative equalization and decoding in a Turbo fashion. We are showing that it is not necessary to run LDPC decoding and equalization as separate entities in a Turbo manner, but integrate decision-feedback equalization (DFE) directly into the LDPC decoder, performing DFE-like operations as part of the LDPC message passing.
Cited by 2
Tadashi Wadayama · IEICE ESS FUNDAMENTALS REVIEW · 2024
本稿では，筆者らが提案したLDPC符号のための近接勾配復号法について解説する．本稿に関する論文 (Wadayama and Takabe, IEICE EA, no.3, pp.359–367, 2023) は，2022年度電子情報通信学会論文賞を受賞した．凸最適化問題を解くための近接勾配法は，スパース信号再構成などの逆問題を解く技法として信号処理分野では広く利用されてきているが，LDPC符号の復号問題への適用はこの論文にて初めて議論がなされた．提案法の核となるアイデアは，通信路に対応する負対数ゆう度と符号に対応する符号ポテンシャルエネルギー関数からなる目的関数に対して，近接勾配法を適用して反復最小化を行うことにより近似的最大事後確率復号を実現する点にある．負対数ゆう度関数を適切に変更することで，広範なクラスの通信路に対して提案復号法を利用することができる．計算機実験の結果，現代の無線通信システムにおいて重要なLDPC符号化MIMO通信路においてデファクトスタンダートである既存手法 (MMSE信号検出とビリーフプロパゲーション復号法の組み合わせ手法) と比較して，提案復号法は顕著な復号性能の改善を与えることが示されている．また，有色ガウス雑音通信路や非線形性を有する通信路など，効率的な復号法の構成が困難である通信路への適用についてもその有効性が実験的に示されている．更に，提案法は，テンソル計算を中心とした実装が可能であり，GPGPU (GeneralPurpose Graphics Programming Unit) やAIアクセラレータなどの深層学習に特化したハードウェアに適した反復構造をもつ．深層展開などの機械学習技術との親和性も高く，今後，実応用に関する研究の進展が期待される．
Cited by 0Open access
Philipp Mohr, Gerhard Bauch · IEEE Communications Letters · 2025
We enhance coarsely quantized LDPC decoding by reusing computed check node messages from previous iterations. Typically, variable and check nodes update and replace old messages every iteration. We show that, under coarse quantization, discarding old messages entails a significant loss of mutual information. The loss is avoided with additional memory, improving performance by up to 0.23 dB. We optimize quantization with a modified information bottleneck algorithm that considers the statistics of old messages. A simple merge operation reduces memory requirements. Depending on channel conditions and code rate, memory assistance enables up to 32% better area efficiency for 2-bit decoding.
Cited by 1Open access
和田山 正, T. Wadayama, 髙邉 賢史 et al. · Tokyo Tech Research Repository (Tokyo Institute of Technology) · 2023
Cited by 0
Mondragon Unibertsitatea · eRepository Mondragon University (Mondragon University) · 2020
Datorren otsailaren 29an, EPFLko Andreas Peter Burg-ek hitzaldi bat emago du Mondragon Unibertsitateko Garaiako Campusean 10:15ean.
Cited by 0Open access
Gabriel Falcão, Vítor Silva, Marco Gomes et al. · 2008
Low-Density Parity-Check (LDPC) codes are among the best error correcting codes known and have been adopted by data transmission standards, such as DVB-S2 or WiMax. They are based on binary sparse parity check matrices and usually represented by Tanner graphs. LDPC decoders require very intensive message-passing algorithms, also known as belief propagation. This paper proposes a very compact stream-based data structure to represent such a bipartite Tanner graph, which supports both regular and irregular codes. This compact data structure not only reduces the memory required to represent the graph but also puts it in an appropriate format to gather data into streams. This representation also allows to map the irregular processing behavior of the Sum Product Algorithm (SPA) used in LDPC decoding into the stream-based computing model. Stream programs were developed for LDPC decoding and the results show significant speedups obtained either using general purpose processors, or graphics processing units. The simultaneous decoding of several codewords was performed using the SIMD capabilities of modern stream-based architectures available on recent processing units.
Cited by 4
Valentin Savin · ArXiv.org · 2007
In this paper we study the impact of the processing order of nodes of a bipartite graph, on the performance of an iterative message-passing decoding. To this end, we introduce the concept of neighborhood reliabilities of graph's nodes. Nodes reliabilities are calculated at each iteration and then are used to obtain a processing order within a serial or serial/parallel scheduling. The basic idea is that by processing first the most reliable data, the decoder is reinforced before processing the less reliable one. Using neighborhood reliabilities, the Min-Sum decoder of LDPC codes approaches the performance of the Sum-Product decoder.
Cited by 2Open access
Tadashi Wadayama, Kensho Nakajima, Ayano Nakai-Kasai · arXiv (Cornell University) · 2023
The power consumption of the integrated circuit is becoming a significant burden, particularly for large-scale signal processing tasks requiring high throughput. The decoding process of LDPC codes is such a heavy signal processing task that demands power efficiency and higher decoding throughput. A promising approach to reducing both power and latency of a decoding process is to use an analog circuit instead of a digital circuit. This paper investigates a continuous-time gradient flow-based approach for decoding LDPC codes, which employs a potential energy function similar to the objective function used in the gradient descent bit flipping (GDBF) algorithm. We experimentally demonstrate that the decoding performance of the gradient flow decoding is comparable to that of the multi-bit mode GDBF algorithm. Since an analog circuit of the gradient flow decoding requires only analog arithmetic operations and an integrator, future advancements in programmable analog integrated circuits may make practical implementation feasible.
Cited by 0Open access
Zhiqiang Cui, Zhongfeng Wang · 2008
In this paper, we propose an extended layered decoding approach for low density parity check (LDPC) codes. Compared to conventional layered decoding algorithms, the proposed approach has no constraint in the column weight of each layer. Hence, it enables more flexibility in high-throughput LDPC decoder design with layered decoding. Simulations on structured and random LDPC codes show that the proposed decoding method achieves significantly faster convergence and slightly better error correction performance than the conventional two phase massage passing sum-product algorithm. We also propose an efficient highly parallel decoder architecture for generic quasi-cyclic LDPC codes to facilitate the practical application of the proposed decoding scheme.
Cited by 5
怡宁 孙, 秋 黄, 剑浩 胡 et al. · Scientia Sinica Informationis · 2022
Due to complexity issues, low-density parity-check (LDPC) codes often use a partial parallel decoding architecture, which cannot easily meet the requirements of high-speed and ultra-high-speed applications. Conversely, the Reed-Solomon (RS) codes often use hard decision decoding algorithms in existing decoding schemes. Therefore, there is room for further optimization in the complexity and performance of concatenated RS -LDPC decoding. In this paper, we propose an RS-LDPC stochastic joint iterative decoding algorithm based on the principle of stochastic computing. This algorithm inherits the advantages of the low complexity of stochastic LDPC decoders and the feature of stochastic RS decoding algorithms, which can use hard decoders. Meanwhile, the decoding performance is improved through the joint iterative decoding architecture. In this respect, we design a test-vector generation method based on LDPC probability values and adopt a novel additional extrinsic information generation mechanism. Such a mechanism is applied to the structure of the variable nodes of the stochastic LDPC decoder. The simulation results show that at a bit error rate of $10^{-6}$, the proposed algorithm can obtain a gain of 0.3 dB as compared with the RS-LDPC cascaded decoding scheme using floating-point belief propagation and Berlekamp -Massey hard decision decoding algorithm. Its implementation complexity is the complexity of a stochastic LDPC decoder and several RS hard decoders. The decoding latency is determined by the latency of the stochastic LDPC decoder. Therefore, the joint iterative decoding algorithm proposed in this paper has a very good application value.
Cited by 0
Julien Du Crest, Francisco García-Herrero, Mehdi Mhalla et al. · arXiv (Cornell University) · 2023
We address the problem of performing message-passing-based decoding of quantum LDPC codes under hardware latency limitations. We propose a novel way to do layered decoding that suits quantum constraints and outperforms flooded scheduling, the usual scheduling on parallel architectures. A generic construction is given to construct layers of hypergraph product codes. In the process, we introduce two new notions, t-covering layers which is a generalization of the usual layer decomposition, and a new scheduling called random order scheduling. Numerical simulations show that the random ordering is of independent interest as it helps relieve the high error floor typical of message-passing decoders on quantum codes for both layered and serial decoding without the need for post-processing.
Cited by 2Open access
Oscar Ferraz, Gabriel Falcão, Vítor Silva · 2024
Low-density parity-check (LDPC) codes play an important role in several communication and storage applications by providing a versatile and efficient solution for correcting errors. Modern computing systems suffer from data movement bottlenecks, which affect parallel processing systems more dramatically. Several solutions to this bottleneck have been proposed by moving compute units where the data resides, incorporating thousands of low-complexity processing units to perform bit-wise and simple integer operations. This paper presents the first known bit flipping LDPC processing-in-memory (PiM)-based decoder in the UPMEM system. The implementation is able to achieve 2.8 Gbit/<tex>$s$</tex> of decoding throughput, which is competitive when compared to implementations in high-end GPUs. The source code can be found at https://github.com/oscarferraz/EUSIPC024
Cited by 4
Oscar Ferraz, Vítor Silva, Gabriel Falcão · IEEE Access · 2025
Low-density parity-check (LDPC) codes are an important feature of several communication and storage applications, offering a flexible and effective method for error correction. These codes are computationally complex and require the exploitation of parallel processing to meet real-time constraints. As advancements in arithmetic and logic unit technology allowed for higher performance of computing systems, memory technology has not kept the same pace of development, creating a data movement bottleneck and affecting parallel processing systems more dramatically. To alleviate the severity of this bottleneck, several solutions have been proposed, namely the processing in-memory (PiM) paradigm that involves the design of compute units to where (or near) the data is stored, utilizing thousands of low-complexity processing units to perform out bit-wise and simple arithmetic operations. This paper presents a novel efficient solution for near-memory non-binary LDPC decoders in the UPMEM system, for the best of our knowledge the first real hardware PiM-based non-binary LDPC decoder that is benchmarked against low-power GPU parallel solutions highly optimized for throughput performance. PiM-based non-binary LDPC decoders can achieve 76 Mbit/s of decoding throughput, which is even competitive when compared against implementations running in edge GPUs.
Cited by 0Open access
Ali Naderi, Shie Mannor, Mohamad Sawan et al. · IEEE Transactions on Signal Processing · 2011
A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 56.5- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at [( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Eb</i> )/( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">No</i> )]=5.5 and 4.8 dB, respectively.
Cited by 136
English &lt;pastel, Hal Id Pastel · 2004
Cited by 0
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang et al. · 2012
Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.
Cited by 4