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About 10,000 papers for “Logic simulation”

Electrical-Logic Simulation

김영환 · Open Access System for Information Sharing (Pohang University of Science and Technology) · 2018

Cited by 0

Sliding window logic simulation

Sarah Thompson, Alan Mycroft · 2004

Existing digital logic simulators typically depend on a discrete-time model of circuit behaviour. Whilst this approach is sufficient in many cases for the validation of the behaviour of synchronous circuits, it is not good at identifying glitches that are narrower than the available time resolution. Moreover, it is not generally feasible to accommodate uncertainty in delay time in such a way as to detect at an early design stage glitches that only occur under worst-case layout-specific or environment dependent timing conditions. This paper presents a technique, based upon abstract interpretation, that, given any synchronous or asynchronous circuit, allows possible glitches to be detected within a particular time window given known starting conditions. Since the underlying model is based upon dense (continuous) time, all possible glitches are detected regardless of how narrow they may be. Adopting a window length equivalent to the worst-case uncertainty in delay, then ‘sliding ’ the window in time such that each successive window overlaps the previous window allows all possible glitches to be identified, without a need for exact timing information. Using this algorithm, it is possible to construct a logic simulator that is capable of automatically detecting possible glitches early in the design life cycle, before layout-specific timing parameters can be determined. 1

Cited by 0

VECTOR-LOGIC FAULT SIMULATION

Vladimir Hahanov, Svetlana Chumachenko, E. I. Lytvynova et al. · Radio Electronics Computer Science Control · 2024

Context. The technological trends of Design&Test computing for the IT industry and academic science are determined by the following directions: in-memory computing, immersive computing, AI computing, focused on energy saving and reduction of computing time when providing services. A mechanism for simulating faults as addresses on smart data structures is proposed, which eliminates the algorithm for simulating input test sets to obtain a test map for logic functionality. The proposed mechanism is focused on the service of SoC IP-cores under the control of the IEEE 1500 standard, which can be perceived positively by engineers in the EDA market. Objective. The purpose of the research is time- and energy-saving mechanisms for simulating malfunctions, such as addresses, by using read-write transactions of in-memory computing to build a test map of any functionality on smart data structures. Method. Smart data structures are represented by a logical vector and its derivatives in the form of truth tables and matrices. The test map is a matrix whose coordinates are determined by the combinations of all logical faults that are tested on the binary sets of the comprehensive test. The construction of the test map is focused on the architecture of in-memory computing based on read-write transactions, which makes the simulation mechanism economical in terms of simulation time and energy consumption due to the absence of a central processor. A logical vector as a single component of input data does not require synthesis into a technologically permitted structure of elements. Synthesis of smart data structures based on four matrix operations creates a fault test map like addresses for any logic. Results. Deductive matrix vectors are effectively used to model faults as addresses in digital structures of any configuration, including convergent branches and feedback loops. The resulting test map is used to find the minimum fault-checking test of the input variables. The proposed fault simulation mechanism technologically easily fits into the architecture of in-memory computing and uses only read-write transactions. The vector logic engine can also be used to test graph structures that are described by a truth table or a logical vector. The truth table addresses used for fault simulation are effectively used for processorless processing of large data in the in-memory computing architecture. Conclusions. Scientific novelty – a vector-logic in-memory computing mechanism for building a test map is proposed, characterized by the construction of intelligent data structures that reset the fault modeling algorithm. The proposed mechanism has no analogues in the design & test industry in terms of simplicity and predictability of data structure sizes and the absence of a test set modeling algorithm. The practical significance is determined by the application of the mechanism for testing logical functionalities of any complexity to solve verification tasks. Prospects of the research – increasing the object of diagnosis to the scheme, i.e. building a test map of the scheme logical structure.

Cited by 1Open access

Statistics on logic simulation

K. F. Wong, Mark A. Franklin, Roger D. Chamberlain et al. · Proceedings of the 23rd ACM/IEEE conference on Design automation - DAC '86 · 1986

The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architecture have the potential for significant speedups over standard software based logic simulators. Several commercial simulation engines have been produced to satisfy need in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. The data contained in the paper includes information on the subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.

Cited by 19Open access

Process Oriented Logic Simulation

S.M. Leinwand · 18th Design Automation Conference · 1981

Theoretically, simulation can be activity oriented, event oriented or process oriented. Existing techniques for logic simulation are either activity or event oriented. In this paper, the possibility of logic simulation using process oriented concepts is investigated. Such an approach is justified by the need to support modular design environments. The key feature is that of asynchronous module activity: the timing order of signal changes has to be preserved only for those events belonging to the same module. It is shown that as long as the proper order of occurence for intermodule signaling is faithfully preserved, a centralized scheduling of events is avoidable. Thus, sequences of uninterruptible local events (termed atomic activities) can be simulated in complete isolation. The correct definition of uninterruptible local activities needs some information on allowable timing of interface events.

Cited by 1

Statistics on Logic Simulation

K. F. Wong, Mark A. Franklin, Roger D. Chamberlain et al. · 23rd ACM/IEEE Design Automation Conference · 1986

The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speedups over standard software based logic simulators. Several commercial simulation engines have been produced to satisfy needs in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. The data contained in the paper includes information on subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.

Cited by 9

A logic simulation machine

M. Abramovici, Y. H. Levendel, P. R. Menon · Proceedings of the nineteenth design automation conference on - DAC '82 · 1982

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.

Cited by 6Open access

Logic Simulation for LSI

K. Hirakawa, N. Shiraki, M. Muraoka · 19th Design Automation Conference · 1982

This paper describes the logic simulation system and the design verification method for logic design, timing analysis, and testing for VLSI. The integrity of test and network data on a logic design stage must be kept in LSI testing in the final verification stage. In dealing with consistency, emphasis is placed on the discrepancy between the real time domain on a simulator and a testing time domain on an LSI tester. The logic simulation system (Block INtegrator and AnaLYzer: BINALY) handles a hierarchical structure, a detailed timing model, and a timing alignment method for a testing time domain.

Cited by 0

Logic-Level Fault Simulation

Raimund Ubar, Jaan Raik, Maksim Jenihhin et al. · Computer science foundations and applied logic · 2024

Cited by 0

Simulation and Hoare Logic

Willem-Paul de Roever, Kai Engelhardt · Cambridge University Press eBooks · 1998

A summary is not available for this content so a preview has been provided. Please use the Get access link above for information on how to access this content.

Cited by 1

DIGITAL LOGIC TESTING AND SIMULATION DIGITAL LOGIC TESTING AND SIMULATION SECOND EDITION

Alexander Miczo, A John Wiley · 2008

Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through

Cited by 0

Parallel distributed-time logic simulation

L. Soule, Aman Gupta · IEEE Design & Test of Computers · 1989

The Chandy-Misra algorithm offers more parallelism than the standard event-driven algorithm for digital logic simulation. With suitable enhancements, the Chandy-Misra algorithm also offers significantly better parallel performance. The authors present methods to optimize the algorithm using information about the large number of global synchronization points, called deadlocks, that limit performance. They classify deadlocks and describe them in terms of circuit structure. The proposed methods that use domain-specific knowledge to avoid deadlocks and present a way to reduce greatly the time it takes to resolve a deadlock. For one benchmark circuit, the authors eliminated all deadlocks using their techniques and increased the average number of logic elements available for concurrent execution from 45 to 160. Simulation results for a 60-processor machine show that the Chandy-Misra algorithm outperforms the event-driven algorithm by a factor of 2 to 15.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 34

Efficient simulation of logic networks

Anwaruddin, 1941-, Anwaruddin, 1941- · UA Campus Repository (The University of Arizona) · 1969

This item was digitized from a paper original. If you need higher-resolution images for any content in this item, please contact us at repository@u.library.arizona.edu.

Cited by 0

Simulation, Ramification, and Linear Logic

White, Graham · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 1998

This article first argues that formalisations of the &amp;quot;frame problem&amp;quot; should have certain desirable logical features; it then proposes a treatment of the frame problem, using linear logic together with modal operators, which fulfils these desiderata and seems to be successful in other respects.

Cited by 0Open access