Marcelino Rodriguez-Cancio, Benoît Combemale, Benoît Baudry · SPIRE - Sciences Po Institutional REpository · 2016
We introduce Approximate Unrolling, a loop optimization that reduces execution time and energy consumption, exploiting the existence of code regions that can endure some degree of approximation while still producing acceptable results. This work focuses on a specific kind of forgiving region: counted loops that map a given functions over the elements of an array. Approximate Unrolling transforms loops in a similar way Loop Unrolling does. However, unlike its exact counterpart, our optimization does not unroll loops by adding exact copies of the loop's body. Instead, it adds interpolations. We describe our experimental implementation of Approximate Unrolling in the Server (C2) Compiler of the Open-JDK Hotspot JVM. The choice to implement our technique directly in the compiler reduced Phase Order problems and transformation overhead. It also proved that our technique could actually improve the performance of a production-ready compiler. Using our modified version of the compiler , we perform several experiments showing that Approximate Unrolling is able reduce execution time and energy consumption of the generated code by a factor of 50% with minimal accuracy losses.
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Jonas Latt (10724968), Christophe Coreixas (10724971), Joël Beny (10724974) · Figshare · 2021
<p>All simulations are executed with the BGK-W2 collision model, with the AA-soa scheme, and with <i>N</i> = 128.</p>
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Shuo Zhang (30844), Yanxia Wu (741216), Chaoguang Men (7484843) et al. · Figshare · 2019
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Meisam Booshehri, Abbas Malekpour, Peter Luksch · arXiv (Cornell University) · 2013
In this paper we review main ideas mentioned in several other papers which talk about optimization techniques used by compilers. Here we focus on loop unrolling technique and its effect on power consumption, energy usage and also its impact on program speed up by achieving ILP (Instruction-level parallelism). Concentrating on superscalar processors, we discuss the idea of generalized loop unrolling presented by J.C. Hang and T. Leng and then we present a new method to traverse a linked list to get a better result of loop unrolling in that case. After that we mention the results of some experiments carried out on a Pentium 4 processor (as an instance of super scalar architecture). Furthermore, the results of some other experiments on supercomputer (the Alliat FX/2800 System) containing superscalar node processors would be mentioned. These experiments show that loop unrolling has a slight measurable effect on energy usage as well as power consumption. But it could be an effective way for program speed up.
Cited by 12Open access
Giridhar Sreenivasa Murthy, M. Ravishankar, Muthu Manikandan Baskaran et al. · OhioLink ETD Center (Ohio Library and Information Network) · 2010
Graphics Processing Units (GPUs) are massively parallel, many-core processors with tremendous computational power and very high memory bandwidth. With the advent of general purpose programming models such as NVIDIA's CUDA and the new standard OpenCL, general purpose programming using GPUs (GPGPU) has become very popular. However, the GPU architecture and programming model have brought along with it many new challenges and opportunities for compiler optimizations. One such classical optimization is loop unrolling. Current GPU compilers perform limited loop unrolling. In this paper, we attempt to understand the impact of loop unrolling on GPGPU programs. We develop a semi-automatic, compile-time approach for identifying optimal unroll factors for suitable loops in GPGPU programs. In addition, we propose techniques for reducing the number of unroll factors evaluated, based on the characteristics of the program being compiled and the device being compiled to. We use these techniques to evaluate the effect of loop unrolling on a range of GPGPU programs and show that we correctly identify the optimal unroll factors. The optimized versions run up to 70 percent faster than the unoptimized versions.
Cited by 67Open access
Marcos De Alba, David R. Kaeli · 2002
General purpose programs contain loops that cannot be optimized by a compiler. When the body of a loop contains conditional control flow instructions or if the loop is controlled by a non-constant induction variable, the compiler again cannot unroll this loop. We have found that the compiler cannot unroll greater than 40-50% of the static loops in the set of programs studied. To be able to optimize the execution these loops, we have to detect loop behavior at runtime.
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Jinyang Yao, Lili Liu, Xuanyu Fu et al. · Research Square · 2024
<title>Abstract</title> SIMD extensions are playing an increasingly important role in high-performance computing and artificial intelligence fields. To fully utilize these components, various manufacturers and institutions have implemented many optimizations for SIMD extensions, with dual SIMD extension pipeline optimization being one of them. This method generates instructions suitable for parallel execution of the integrated dual SIMD extension on processors by unrolling vectorizable loops in programs. It is integrated into a mainstream compiler GCC as an optimization pass and can be enabled with just one compilation option. Experiments were conducted on an SW421 processor, testing standard benchmark suites such as SPEC CPU 2006 and NPB. The experiments showed that after using this optimization pass, programs generated by the compiler can fully utilize the dual SIMD extension during execution. Compared with turning on the autovectorization option, the method has an acceleration effect on multiple applications in the test set, and the execution efficiency is improved by an average of 5.6% and a maximum of 14%.
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Karim Soliman, Marwa El Shenawy, Ahmed A. El Farag · 2018
Parallel code optimization has many challenges to improve the code performance. Loop unrolling is an optimization technique applied to the loops to reduce the frequency of branches. This optimization is a useful technique to enhance the performance of the applications especially with the increase of pipeline depth in modern processors. The proposed approach is to perform the loop unrolling optimization over understudied problems Sparse Dense Matrix Multiplications SpDM, and Dense Matrix Multiplication with cache oblivious algorithm using Peano Curves, and measure the effects on both sequential and parallel execution.
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Frank Hannig, Hritam Dutta, Jürgen Teich · Lecture notes in computer science · 2009
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David Sánchez-Charles, Marc Solé, Josep Carmona et al. · 2016
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Goran Velkoski, Marjan Gušev, Sasko Ristov · 2014
Loop unrolling is a well known technique, which usually results with speedup of a program that contains loops. The effect is obtained by reducing the operations that require counter increases and branch jumps at the end of the loops. This paper analyzes the impact of loop unrolling on various processor types and memory patterns. The experiments show a high correlation between the cache and the problem size. The loop unrolling results with a higher speedup for the execution of a smaller size problem, while it does not have impact for a problem whose size is greater than the capacity of the last level cache size, due to the huge number of cache misses. Another important result is that the loop unrolling achieves greater speedup on Intel, rather than AMD CPU. In this paper we analyze and discuss the various behaviors of loop unrolling.
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Nicholas Nethercote, Doug Burger, Kathryn S. Mckinley · 2006
Abstract. Well-engineered compilers use a carefully selected set of optimizations, heuristic optimization policies, and a phase ordering to produce good machine code. Designing a compiler with one heuristic per optimization that works well with other optimization phases is a challenging task. Although compiler designers evaluate the optimization heuristics and phase ordering before deployment, compilers typically do not statically evaluate nor refine the quality of their optimization decisions during a specific compilation. This paper identifies a class of optimizations for which the compiler can evaluate the effectiveness of its heuristics and phase interactions statically, and when necessary re-run optimization phases, using information from the evaluation phase to guide its heuristics. We call this approach self-evaluating compilation (SEC). This model avoids some of the difficulties of predicting phase interactions, and perfecting any one heuristic. The SEC model was motivated by loop unrolling and other optimizations
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Francisco J Soulignac, Pablo Terlisky · arXiv (Cornell University) · 2022
A proper circular-arc (PCA) model is a pair $M = (C, A)$ where $C$ is a circle and $A$ is a family of inclusion-free arcs on $C$ whose extremes are pairwise different. The model $M$ represents a digraph $D$ that has one vertex $v(a)$ for each $a \in A$ and one edge $v(a) \to v(b)$ for each pair of arcs $a,b \in A(M)$ such that the beginning point of $b$ belongs to $a$. For $k \geq 0$, the $k$-th power $D^k$ of $D$ has the same vertices as $D$ and $v(a) \to v(b)$ is an edge of $D^k$ when $a\neq b$ and the distance from $v(a)$ to $v(b)$ in $D$ is at most $k$. A unit circular-arc (UCA) model is a PCA model $U = (C,A)$ in which all the arcs have the same length $\ell+1$. If $\ell$, the length $c$ of $C$, and the extremes of the arcs of $A$ are integer, then $U$ is a $(c,\ell)$-CA model. For $i \geq 0$, the model $i \times U$ of $U$ is obtained by replacing each arc $(s,s+\ell+1)$ with the arc $(s,s+i\ell+1)$. If $U$ represents a digraph $D$, then $U$ is $k$-multiplicative when $i \times U$ represents $D^i$ for every $0 \leq i \leq k$. In this article we design a linear time algorithm to decide if a PCA model $M$ is equivalent to a $k$-multiplicative UCA model when $k$ is given as input. The algorithm either outputs a $k$-multiplicative UCA model $U$ equivalent to $M$ or a negative certificate that can be authenticated in linear time. Our main technical tool is a new characterization of those PCA models that are equivalent to $k$-multiplicative UCA models. For $k=1$, this characterization yields a new algorithm for the classical representation problem that is simpler than the previously known algorithms.
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Giridhar Sreenivasa Murthy · 2010
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Vojdan Stefkovski, Dimitar Mileski, Marjan Gušev · 2024
This paper investigates the impact of loop unrolling on CUDA matrix multiplication operations’ performance across NVIDIA GPUs. We benchmarked both basic and unrolled kernels with varying unroll factors (2, 4, 8, and 16) and CUDA block sizes (8, 16, and 32) on matrices ranging from 128 × 128 to 4096 × 4096. Using two GPUs, the GeForce RTX 4060 and GTX TITAN X, we analyze how unrolling factors impact execution time. Our findings indicate that loop unrolling, particularly with factors of 8 and 16 and a block size of 32, yields significant performance gains on larger matrices. These results confirm loop unrolling as an effective optimization technique for CUDA matrix operations, providing insights for developers to enhance computational efficiency across different GPU architectures.
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Sid Touati, Benoît Dupont de Dinechin · 2014
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Takeshi Matsumoto, Kenshu Seto, Masahiro Fujita · Medical Entomology and Zoology · 2007
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Narasinga Rao Miniskar, Pankaj Shailendra Gode, Soma Kohli et al. · 2012
The next generation SoCs for consumer electronics need software solutions for faster time-to-market, lower development cost and higher performance while maintaining lower energy consumption and area. As a result, reconfigurable processors (RPs) have become increasingly important, which enables just enough exibility of accepting software solutions and providing application-specific hardware reconfigurability. Samsung Electronics has developed a reconfigurable processor called Samsung Reconfigurable Processor (SRP), which is the basis of our work. Though, the SRP is a powerful processor, it requires a smart and intelligent compiler to compile the application software while exploring its reconfigurable architecture. The existing compiler for the SRP does not support functional inlining and loop unrolling, and no study has yet been done on these optimizations for the RPs. In this paper, we study the impact of these optimizations on the performance of applications for the SRP processor and we also show how these optimizations are supported in the SRP compiler. We analyze the performance improvement due to these optimizations on various benchmarks namely Sobel Edge filter, JPEG decoder, and Luma Deblocking filter of the H.264 standard. Our experimental results have shown about 83% gain on performance with the functional inlining optimization and the loop unrolling optimization when compared to the original code for Sobel filter and JPEG encoder, and 11% gain on performance for Luma Deblock filter.
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Hesham El‐Rewini, Hesham Ali · Parallel algorithms and applications · 1995
In this paper, we study the problem of scheduling loop task graphs onto two processor systems to minimize the execution lime. We use the idea of loop unrolling to uncover dependence among different loop iterations in loop task graphs. The scheduling is divided into two stages: determining an optimal unrolling factor, and constructing an optimal schedule for this unrolling factor. We propose a criterion for optimal loop unrolling for unit-delay task graphs, where the tasks are enclosed in a single loop. Our main theorem presents a useful test for detecting optimal unrolling factors. A scheduling algorithm that employs the concept of optimal loop unrolling is introduced. We also present serial and parallel algorithms lo find the best unrolling factor.
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J. C. Huang, T. Leng · 2003
It is well known that to optimize a program for speedup efforts should be focused on the regions where the payoff will be greatest. Loop constructs in a program represent such regions. In the literature, it has been shown that a certain degree of speedup can be achieved by loop unrolling. The technique published so far, however, appears to be applicable to FOR-loops only. This paper presents a generalized loop-unrolling method that can be applied to any type of loop construct. Possible complications in its applications, together with some experimental results, are discussed in detail.
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