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About 10,000 papers for “Many core”

Many-Core Levels

Hijma, Pieter, Jacobs, Ceriel · Figshare · 2019

Many-Core Levels (MCL) is a framework that allows one to write computational kernels for different kinds of many-core hardware

Cited by 0Open access

Many-Core Levels

Hijma, Pieter, Jacobs, Ceriel · Figshare · 2019

Many-Core Levels (MCL) is a framework that allows one to write computational kernels for different kinds of many-core hardware

Cited by 0Open access

Many-task computing on many-core architectures

Hoffman, J., Jansson, J., Jansson, N. · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2016

Developing multiphysics finite element methods (FEM) and scalable HPC implementations can be very challenging in terms of software complexity and performance, even more so with the addition of goal-oriented adaptive mesh refinement. To manage the complexity we in this work present general adaptive stabilized methods with automated implementation in the FEniCS-HPC automated open source software framework. This allows taking the weak form of a partial differential equation (PDE) as input in near-mathematical notation and automatically generating the low-level implementation source code and auxiliary equations and quantities necessary for the adaptivity. We demonstrate new optimal strong scaling results for the whole adaptive framework applied to turbulent flow on massively parallel architectures down to 25000 vertices per core with ca. 5000 cores with the MPI-based PETSc backend and for assembly down to 500 vertices per core with ca. 20000 cores with the PGAS-based JANPACK backend. As a demonstration of the power of the combination of the scalability together with the adaptive methodology allowing prediction of gross quantities in turbulent flow we present an application in aerodynamics of a full DLR-F11 aircraft in connection with the HiLift-PW2 benchmarking workshop with good match to experiments.

Cited by 0Open access

Many-Task Computing on Many-Core Architectures

Pedro Valero‐Lara, Poornima Nookala, Fernando L. Pelayo et al. · Scalable Computing Practice and Experience · 2016

Many-Task Computing (MTC) is a common scenario for multiple parallel systems, such as cluster, grids, cloud and supercomputers, but it is not so popular in shared memory parallel processors. In this sense and given the spectacular growth in performance and in number of cores integrated in many-core architectures, the study of MTC on such architectures is becoming more and more relevant. In this paper, authors present what are those programming mechanisms to take advantages of such massively parallel features for the particular target of MTC. Also, the hardware features of the two dominant many-core platforms (NVIDIA GPUs and Intel Xeon Phi) are also analyzed for our specific framework. Given the important differences in terms of hardware and software in our two many-core platforms, we have considered different strategies based on CUDA (for GPUs) and OpenMP (for Intel Xeon Phi). We carried out several test cases based on an appropriate and widely studied problem for benchmarking as matrix multiplication. Essentially, this study consisted of comparing the time consumed for computing in parallel several tasks one by one (the whole computational resources are used just to compute one task at a time) with the time consumed for computing in parallel the same set of tasks simultaneously (the whole computational resources are used for computing the set of tasks at very same time). Finally, we compared both software-hardware scenarios to identify the most relevant computer features in each of our many-core architectures.

Cited by 15Open access

Multi-core and many-core processors.

Andrea Manconi (566020), Alessandro Orro (28770), Emanuele Manca (566021) et al. · Figshare · 2015

<p>Multi-core processors as CPUs are devices composed of few cores with lots of cache memory able to handle a few software threads at a time. Conversely, many-core processors as GPUs are devices equipped with hundreds of cores able to handle thousands of threads simultaneously.</p>

Cited by 0Open access

Many-core compiler fuzzing

Christopher Lidbury, Andrei Lascu, Nathan Chong et al. · 2015

We address the compiler correctness problem for many-core systems through novel applications of fuzz testing to OpenCL compilers. Focusing on two methods from prior work, random differential testing and testing via equivalence modulo inputs (EMI), we present several strategies for random generation of deterministic, communicating OpenCL kernels, and an injection mechanism that allows EMI testing to be applied to kernels that otherwise exhibit little or no dynamically-dead code. We use these methods to conduct a large, controlled testing campaign with respect to 21 OpenCL (device, compiler) configurations, covering a range of CPU, GPU, accelerator, FPGA and emulator implementations. Our study provides independent validation of claims in prior work related to the effectiveness of random differential testing and EMI testing, proposes novel methods for lifting these techniques to the many-core setting and reveals a significant number of OpenCL compiler bugs in commercial implementations.

Cited by 145

Many-core virtual machines

Stefan Marr, Theo D’Hondt · 2010

We propose to search for common abstractions for concurrency models to enable multi-language virtual machines to support a wide range of them. This would enable domain-specific solutions for concurrency problems. Furthermore, such an abstraction could improve portability of virtual machines to the vastly different upcoming many-core architectures.

Cited by 2

Accelerator Many-Core Processors

Stephen Michell, Brad Moore, Luis Miguel Pinho et al. · 2016

Multi-core platforms are challenging the way software isdeveloped, in all application domains. For the particular case ofreal-time systems, models for the development of parallelsoftware must be able to be shown correct in both functional andnon-functional properties at design-time. In particular, issues suchas concurrency, timing behaviour and interaction with theenvironment need to be addressed with the same caution as for thefunctional requirements. This paper proposes an execution model for the parallelization ofreal-time software, based upon a fine-grained parallelism supportbeing proposed to Ada, a programming language particularlysuited to the development of critical, concurrent software. Wealso show the correctness of the proposed model in terms ofsatisfying constraints related to execution order and unboundedpriority inversions. © CISTER Research Center www.cister.isep.ipp.pt

Cited by 0

Modelling many-core architectures

Guihai Yan, Jiajun Li, Xiaowei Li · Institution of Engineering and Technology eBooks · 2019

Architectural modelling has two primary objectives: (1) navigating the design space exploration, i.e. guiding the architects to arrival at better design choices, and (2) facilitating dynamic management, i.e. providing the functional relationships between workloads'characteristics and architectural configurations to enable appropriate runtime hardware/software adaptations. In the past years, many-core architectures, as a typical computing fabric evolving from the monolithic single-/multicore architectures, have been shown to be scalable to uphold the staggering the Moore's Law. The many-core architectures enable two orthogonal approaches, scale-up and scale-out, to utilize the growing budget of transistors. Understanding the rationale behind these approaches is critical to make more efficient use of the powerful computing fabric.

Cited by 0

MANY-CORE FRAGMENTATION SIMULATION

ANDREI ALHADEFF MONTEIRO · 2011

[pt] Apresentamos um método computacional na GPU que lida com eventos de fragmentação dinâmica, simulados por meio de elementos de zona coesiva. O trabalho é dividido em duas partes. Na primeira parte, tratamos o pré-processamento de informações e a verificação de corretude e eficácia da inserção dinâmica de elementos coesivos em malhas grandes. Para tal, apresentamos uma simples estrutura de dados topológica composta de triângulos. Na segunda parte, o código explícito de dinâmica é apresentado, que implementa a formulação extrínsica de zona coesiva, onde os elementos são inseridos dinamicamente quando e onde forem necessários. O principal desafio da implementação na GPU, usando a formulação de zona coesiva extrínsica, é ser capaz de adaptar dinamicamente a malha de uma forma consistente, inserindo elementos coesivos nas facetas fraturadas. Para isso, a estrutura de dados convencional usada no código de elementos finitos (baseado na incidência de elementos) é estendida, armazenando, para cada elemento, referências para elementos adjacentes. Para evitar concorrência ao acessar entidades compartilhadas, uma estratégia convencional de coloração de grafos é adotada. Na fase de pré-processamento, cada nó do grafo (elementos na malha) é associado a uma cor diferente das cores de seus nós adjacentes. Desta maneira, elementos da mesma cor podem ser processados em paralelo sem concorrência. Todos os procedimentos necessários para a inserção de elementos coesivos nas facetas fraturadas e para computar propriedades de nós são feitas por threads associados a triângulos, invocando um kernel por cor. Computações em elementos coesivos existentes também são feitas baseadas nos elementos adjacentes.

Cited by 0Open access

Many-Core Graph Workload Analysis

Stijn Eyerman, Wim Heirman, Kristof Du Bois et al. · 2018

Graph applications have specific characteristics that are not common in other application domains and therefore require thorough analysis to guide future graph processing hardware design. In this paper, we analyze multiple graph applications on current multi and many-core processors, and provide conclusions and recommendations for future designs. We restate well-known characteristics of graph applications, such as a low compute to memory ratio and irregular memory access patterns, but we also provide new important insights on executing graph applications on many-core processors. Our main novel observations are (i) some memory streams do show locality, while others show no locality, (ii) thread imbalance becomes a major problem with many threads, and (iii) many threads are required to saturate high-bandwidth memories. The first observation calls for a selective memory access policy, where accesses with locality are cached and prefetched, while accesses without locality can remain uncached to save cache capacity, and can fetch only one element from memory instead of a full cache line to save on memory bandwidth. The last two observations are contradicting: more threads are needed, but they are not used efficiently due to thread imbalance. Our recommendation is therefore to thoroughly revise the graph analysis algorithms to provide more scalable parallelism to be able to exploit the potential of many-core architectures with high-bandwidth memory. In addition, providing a few high-performance cores can speed up sections with low parallelism.

Cited by 23

Ada and many-core platforms

Luís Miguel Pinho, Stephen Michell, Brad Moore · ACM SIGAda Ada Letters · 2013

The new many-core platforms make it difficult for the programmer to provide efficient mapping of Ada programs onto the underlying non-uniform hardware. This paper discusses how existing Ada concepts such as Dispatching Domains and the Distributed Systems Annex can be extended or changed to better support the hierarchical and heterogeneous nature of these platforms.

Cited by 1

Cashmere: Heterogeneous Many-Core Computing

Pieter Hijma, Ceriel J. H. Jacobs, Rob V. van Nieuwpoort et al. · 2015

New generations of many-core hardware become available frequently and are typically attractive extensions for data-centers because of power-consumption and performance benefits. As a result, supercomputers and clusters are becoming heterogeneous and start to contain a variety of many-core devices. Obtaining performance from a homogeneous cluster-computer is already challenging, but achieving it from a heterogeneous cluster is even more demanding. Related work primarily focuses on homogeneous many-core clusters. In this paper we present Cashmere, a programming system for heterogeneous many-core clusters. Cashmere is a tight integration of two existing systems: Satin is a programming system that provides a divide- and-conquer programming model with automatic load-balancing and latency-hiding, while Many-Core Levels is a programming system that provides a powerful methodology to optimize computational kernels for varying types of many-core hardware. We evaluate our system with several classes of applications and show that Cashmere achieves high performance and good scalability. The efficiency of heterogeneous executions is comparable to the homogeneous runs and is >90% in three out of four applications.

Cited by 12

Many-core graph workload analysis

Stijn Eyerman, Wim Heirman, Kristof Du Bois et al. · 2018

Graph applications have specific characteristics that are not common in other application domains and therefore require thorough analysis to guide future graph processing hardware design. In this paper, we analyze multiple graph applications on current multi and many-core processors, and provide conclusions and recommendations for future designs. We restate well-known characteristics of graph applications, such as a low compute to memory ratio and irregular memory access patterns, but we also provide new important insights on executing graph applications on many-core processors. Our main novel observations are (i) some memory streams do show locality, while others show no locality, (ii) thread imbalance becomes a major problem with many threads, and (iii) many threads are required to saturate high-bandwidth memories. The first observation calls for a selective memory access policy, where accesses with locality are cached and prefetched, while accesses without locality can remain uncached to save cache capacity, and can fetch only one element from memory instead of a full cache line to save on memory bandwidth. The last two observations are contradicting: more threads are needed, but they are not used efficiently due to thread imbalance. Our recommendation is therefore to thoroughly revise the graph analysis algorithms to provide more scalable parallelism to be able to exploit the potential of many-core architectures with high-bandwidth memory. In addition, providing a few high-performance cores can speed up sections with low parallelism.

Cited by 6

Benchmarking SW26010 Many-Core Processor

Zhigeng Xu, James Lin, Satoshi Matsuoka · 2017

Equipped with the Chinese home-grown SW26010 many-core processor, TaihuLight claims the top place in the TOP500 list released in June 2016. Although some large-scale applications have been successfully running on the supercomputer, few studies have been conducted to analyze the performance impact caused by the extreme memory-bound architecture design. To facilitate native in-depth optimizations and performance modeling, understanding the architecture and performance characteristics of SW26010 is essential. Therefore, we developed a suite of micro-benchmarks written in C/assembly and characterized the key architectural components: (1) the pipelines of computing processing elements; (2) the softwarecontrolled memory hierarchy; and (3) the lightweight onchip communication at register level. Our benchmark results indicate that the comprehensive optimizations from highlevel algorithm design to low-level instruction scheduling are required to achieve good performance on SW26010.

Cited by 51