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About 10,000 papers for “Memory bandwidth”
John Shalf, Grows Year · 2012
• � Cautionary tales of results that seemed obvious, but turned out not to be –�Memory bandwidth and the “multi-core penalty ” (NOT!) –�Multicore penalty “the sequel” –�OS Interference: “The case of the missing supercomputer performance ” (NOT!) 1 � Memory Performance is Key Ever-growing processor-memory performance gap
Cited by 0
Sanyam Mehta · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023
A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer ("ORB"). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
Cited by 0Open access
Sumit Gulwani, Fixpoint Brush · 2012
Bounding such resources is important. • Economic reasons • Environment might have hard resource constraints. Bounding such resources requires computing bound on # of visits to control-locations that consume such resources.
Cited by 0
Di Xu, Chenggang Wu, Pen-Chung Yew · 2010
Shared-memory multiprocessors have dominated all platforms from high-end to desktop computers. On such platforms, it is well known that the interconnect between the processors and the main memory has become a major bottleneck. The bandwidth-aware job scheduling is an effective and relatively easy-to-implement way to relieve the bandwidth contention. Previous policies understood that bandwidth saturation hurt the throughput of parallel jobs so they scheduled the jobs to let the total bandwidth requirement equal to the system peak bandwidth. However, we found that intra-quantum fine-grained bandwidth contention still happened due to a program's irregular fluctuation in memory access intensity, which is mostly ignored in previous policies.
Cited by 76
David Herres · 2020
Cited by 0
David Eklöv, Nikos Nikoleris, David Black-Schaffer et al. · 2012
Applications that are co-scheduled on a multicore compete for shared resources, such as cache capacity and memory bandwidth. The performance degradation resulting from this contention can be substantial, which makes it important to effectively manage these shared resources. This, however, requires insight into how applications are impacted by such contention. In this paper we present a quantitative method to measure applications' sensitivities to different degrees of contention for off-chip memory bandwidth on real hardware. This method is then used to demonstrate the varying contention sensitivity across a selection of benchmarks, and explains why some of them experience substantial slowdowns long before the overall memory bandwidth saturates.
Cited by 13
Michał Piotr Podleś, Idelfonso Tafur Monroy, Juan José Vegas Olmos et al. · Lecture notes in computer science · 2026
Cited by 0
Xuzhen He (14676114) · Figshare · 2023
Cited by 0Open access
Raghu Sreeramaneni, Lie‐Liang Yang, Remco Chang et al. · 2025
High-Bandwidth-Memory (HBM) technology is powering the accelerated computing and GPUs behind the AI revolution. This paper discusses the important role HBM architecture, performance, power, capacity, and RAS play in AI hardware. We will compare the HBM memory architecture with more traditional compute memory such as DDR5 focusing on Micron Technology's industry-leading HBM3E. We will end with a look towards the future technology innovations that will be essential to deliver continued HBM scaling.
Cited by 1
S. Arash Ostadzadeh, Marco Corina, Carlo Galuzzi et al. · 2010
One of the main issues in heterogeneous reconfigurable computing is the well-known processor/memory bottleneck. Due to the memory bandwidth limitations, the performance of execution of an application can dramatically increase via the efficient usage of the memory. In this paper, we present tQUAD, a new tool for the memory bandwidth usage analysis. This tool is capable of delivering detailed temporal memory bandwidth usage information for the functions in an application throughout a comprehensive analysis of the memory access patterns of individual functions. This tool, first in its kind, provides an accurate analysis of the task execution and memory bandwidth usage which in the end leads to a sophisticated partitioning of the tasks into different phases during the execution span of an application. Together with an accurate description of the tool, the paper presents a real case study from the multimedia domain to detail all features of the proposed tool.
Cited by 6
Sunyoung Hwang, Wonjung Lee, Eojin Lee · Journal of KIISE · 2026
최근 대용량 메모리 수요가 급증에 따라 CXL 기반의 계층형 메모리 구조가 주목받고 있다. 기존 대부분의 계층형 메모리 관리 방식은 활용도가 낮은 cold 데이터를 느린 메모리에 배치하는데, 이는 대역폭 요구가 높은 상황에서는 오히려 시스템 성능 하락을 유발할 수 있다. 본 논문에서는 이를 해결하기 위해 대역폭 인식 메모리 마이그레이션(Bandwidth-Aware Memory Migration, BAMM)을 제안한다. BAMM은 시스템의 메모리 및 대역폭 활용 상태를 실시간으로 관찰하며, 대역폭 요구가 높은 경우 cold 데이터가 아닌 일정 수준의 접근이 존재하는 데이터를 선택적으로 이주시켜 느린 메모리의 대역폭 활용률을 높인다. 실험 결과, BAMM은 대역폭 요구가 높은 워크로드에서 평균 11.22%, 최대 27.11%의 성능 향상과 기존 메모리 관리 방식 대비 평균 18.29 GB/s, 최대 33.48 GB/s의 시스템 전체 대역폭 사용량 증가를 달성하였다.
Cited by 0
K. Reim, Joshua Nunn, Virginia O. Lorenz et al. · 2010
We demonstrate the coherent storage and retrieval of sub-nanosecond low-intensity light pulses with spectral bandwidths exceeding 1 GHz in cesium vapor, using the novel, far off-resonant two-photon Raman memory protocol.
Cited by 0
H.F. Li · Proceedings of the IEEE · 1980
A Markov chain analysis is presented for evaluating the average memory bandwidth of a multiple microprocessor system where the random access memory modules have a cycle time shorter than the processor cycle time. The results are useful in the design of such systems, as well as in the understanding of the effects of such processor-memory speed mismatches.
Cited by 6
Miguel A. Delgado, Peter M. Robinson · London School of Economics and Political Science Research Online (London School of Economics and Political Science) · 1996
For long range dependent time series with a spectral singularity at frequency zero, a theory for optimal bandwidth choice in non-parametric analysis ofthe singularity was developed by Robinson (1991b). The optimal bandwidths are described and compared with those in case of analysis of a smooth spectrum. They are also analysed in case of fractional ARIMA models and calculated as a function of the self similarity parameter in some special cases. Feasible data dependent approximations to the optimal bandwidth are discussed.
Cited by 71Open access
Joseph W. Goodman · SPIE eBooks · 2026
Chapter 5 traces the evolution of solid-state memory, highlighting exponential growth in capacity and bandwidth driven by Moore’s law and key innovations. Early computers like ENIAC relied on vacuum tubes, offering only 83 bytes of storage. Magnetic core memory dominated until the mid-1970s, followed by SRAM for speed-critical tasks. The pivotal breakthrough came with DRAM, invented by Robert Dennard in 1968, with Intel’s 1103 chip debuting in 1970. DRAM’s simple design—one transistor and one capacitor per cell—enabled high density and low cost, though periodic refresh was required. Successive milestones included CMOS DRAM (1979), synchronous DRAM (1992), and DDR SDRAM (2000), which doubled data transfer rates. Later generations (DDR2–DDR5) and high-bandwidth memory (HBM) introduced 3D stacking and through-silicon vias, vastly improving performance for data-intensive applications. Both capacity and bandwidth have grown exponentially, making modern memory essential for high-performance computing and graphics.
Cited by 0
Charles Y. Hitchcock, Sally A. Mckee, Sally A. Mckee et al. · 1993
Cited by 0
Carey Kloss · 2017
No abstract available.
Cited by 0
Doug Burger, James Goodman, Alain Kägi · ACM SIGARCH Computer Architecture News · 1996
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the expense of increased bandwidth requirements. Using a decomposition of execution time, we show that for modern processors that employ aggressive memory latency tolerance techniques, wasted cycles due to insufficient bandwidth generally exceed those due to raw memory latencies. Given the importance of maximizing memory bandwidth, we calculate effective pin bandwidth, then estimate optimal effective pin bandwidth. We measure these quantities by determining the amount by which both caches and minimal-traffic caches filter accesses to the lower levels of the memory hierarchy. We see that there is a gap that can exceed two orders of magnitude between the total memory traffic generated by caches and the minimal-traffic caches---implying that the potential exists to increase effective pin bandwidth substantially. We decompose this traffic gap into four factors, and show they contribute quite differently to traffic reduction for different benchmarks. We conclude that, in the short term, pin bandwidth limitations will make more complex on-chip caches cost-effective. For example, flexible caches may allow individual applications to choose from a range of caching policies. In the long term, we predict that off-chip accesses will be so expensive that all system memory will reside on one or more processor chips.
Cited by 56Open access
W. Miksad, William A. Wulf (dissertation Advisor, Jack W. Davidson (committee Chair et al. · 1995
Cited by 0
David López, Mateo Valero, Josep Llosa et al. · 1997
Article Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs Share on Authors: David López Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, Spain Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, SpainView Profile , Mateo Valero Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, Spain Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, SpainView Profile , Josep Llosa Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, Spain Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, SpainView Profile , Eduard Ayguadé Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, Spain Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Campus Nord, Mòdul D6, Jordi Girona 1-3, 08034 Barcelona, SpainView Profile Authors Info & Claims ICS '97: Proceedings of the 11th international conference on SupercomputingJuly 1997 Pages 12–19https://doi.org/10.1145/263580.263585Online:11 July 1997Publication History 10citation232DownloadsMetricsTotal Citations10Total Downloads232Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Cited by 13