Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 7,464 papers for “Memory controller”

Memory Controller Methodology

D-stacked Drams, Manil Dev Gomony, Benny Åkesson et al. · 2016

Devise different DRAM architecture solutions using 3D-Integration technology for improved bandwidth and evaluate the real-time performance in terms of memory efficiency and bandwidth. Proposed architecture We consider a Parallel-Access (PA) method in which each bank of the DRAM has its own command and data interface to the memory controller. This approach is about using the 3D-Integration technology enabler to make banks into independent memories by removing shared logic meant to reduce the number of pins. This increases the provided bandwidth.

Cited by 0

Memory node controller

Jonathan Curtis Beard · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

Cited by 0Open access

Latency-agnostic memory controller

Philip Emma · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Cited by 0Open access

Memory Controller for GPU

Seyhanli, Özgür · QRU Quaderns de Recerca en Urbanisme · 2015

I implemented memory controller to the GPU simulation of Multi2Sim simulator. The memory controller offers 2 different scheduling options in order to improve the efficiency of the simulator.

Cited by 0Open access

Memory Controller Block Startup

Xilinx Sp Board, Spartan- Memory, Controller Block · 2009

� Dedicated Memory Controller Blocks (MCB) for Simplified DRAM interfaces – Up to 4 MCB cores in a single Spartan-6 device – Embedded controller and physical (PHY) interface – Supports 4-bit, 8-bit, or 16-bit single component memory – Memory densities up to 4 Gbit � Performance up to 667 Mb/s (333 MHz double data rate) � Configurable dedicated Multi-port user interface to FPGA logic – 1 to 6 ports per MCB depending on configuration – Internal 32-, 64-, or 128-bit data bus optionsNote: Presentation applies to the SP601 MCB Block Diagram � Simple User Interface abstracts away complexity of memory transactions � MIG / EDK wrapper delivers complete interface solution – Internal block assembly and signal connectivity is made transparent to the userNote: Presentation applies to the SP601

Cited by 0

Mitigating Memory Controller Side Channels

Deutsch, Peter William · DSpace@MIT (Massachusetts Institute of Technology) · 2022

Memory timing side channels, where attackers utilize contention within DRAM controllers to infer a victim’s secrets, pose an important challenge to secure computation in shared memory environments. Attacks utilizing these side channels are broad and highly effective, as memory controllers offer a shared attack surface across all cores on a machine. Attacks have been demonstrated in the wild to leak cryptographic keys and other secret data, emphasizing the importance of employing mitigations to block the ability of an attacker to leak information. Existing state-of-the-art memory timing side channel mitigations have several key performance and security limitations. Prior schemes require onerous static bandwidth partitioning, extensive profiling phases, or simply fail to protect against attacks which exploit fine-grained timing and bank information. In this thesis we present DAGguise, a defense mechanism which fully protects against memory timing side channels while allowing for dynamic traffic contention in order to achieve good performance. DAGguise utilizes a novel abstract memory access representation, the Directed Acyclic Request Graph (rDAG for short), to model memory access patterns which experience contention. DAGguise shapes a victim’s access patterns according to a publicly known rDAG obtained through a lightweight profiling stage, completely eliminating information leakage. We formally verify the security of DAGguise, proving that it maintains strong security guarantees. Moreover, by allowing dynamic traffic contention, DAGguise achieves a 12% overall system speedup relative to Fixed Service, which is the state-of-the-art mitigation mechanism, with up to a 20% relative speedup for co-located applications which do not require protection. We further claim that the principles of DAGguise can be generalized to protect against other types of scheduler-based timing side channels, such as those targeting on-chip networks, or functional units in SMT cores.

Cited by 0

Access-rate guaranteed memory controller

Morral Escofet, Berta · Lund University Publications Student Papers (Lund University) · 2018

On-chip memory plays an important role in system-on-chip (SoCs) being in most cases the dominant part in both area and power. Additionally, it determines the overall system's speed. As a result, new memory architectures and technologies have been developed over the years in order to improve the overall system performance. This project introduces the design and implementation of a memory controller algorithm that increases the throughput while guaranteeing a fix access-rate of the memory. The work is focused on incrementing the number of read operations, i.e., being capable of performing two-read operation per clock cycle, with the use of single-port memory banks. Three different algorithms are implemented (XOR solution, Word Addition solution (WA), and Bit Addition solution (BA)) and are compared in terms of area, power and speed. Moreover, they are compared to the conventional two-port memory solution. In addition, a simple BIST (built-in self-test) engine has been implemented in order to perform a basic functionality test in memory. The BIST module is integrated into the Word Addition solution. The project concludes that the area per bit of the three solutions decreases as the size of the memory increases. However, it is by increasing the number of rows that the lowest cell area per bit values are achieved. The three solutions reduce the power and the area compared to the conventional two-port memory solution, with the XOR solution being the most area and power efficient. Even though the area and power increase between solutions is significant, when considering the memory block system (memory controller and memory banks), the overall area and power difference is negligible. Moreover, the three solutions have shown to be able to work at higher speeds than conventional 28nm SRAM. Also, the system with the integrated BIST into the memory controller has an area and power significantly smaller compared to the conventional two-port memory solution. Finally, the memory controller speed is not affected by the BIST.

Cited by 0Open access

RAMON: Region-Aware Memory Controller

Mário Donato Marino, Kuan‐Ching Li · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2018

Recent implementations of heterogeneous multicore systems [central processing unit (CPU), graphics processing unit (GPU), and hybrid] address the issue of communication latency between CPU and GPU memory systems by merging these two, so that they can share the same memory address space. In recent years, the combination of the escalation in the number of cores with the rise in memory-intensive applications has significantly increased bandwidth (Bw) needs in both homogeneous and heterogeneous systems. Since tasks assigned to CPU and/or GPU cores will have different Bw demands, a two-tier memory system is needed. Hence, in this paper, Region-Aware Memory cONtroller (RAMON) is proposed as a configurable memory system where different address space regions are able to be dedicated to a different number of memory controllers (MCs), concurrently to supply different amounts of Bw to a different number of cores, providing different levels of memory parallelism. By having different address space regions-simply regions, each with a different number of MCs to match its Bw needs, memory interference per region is reduced. Our findings show that RAMON is promising and improves Bw by a factor of 9 times for CPU regions, 14.1 times for GPU regions, and 4.5 times for combined heterogeneous regions.

Cited by 8Open access

Access-rate guaranteed memory controller

Berta Morral Escofet · 2018

On-chip memory plays an important role in system-on-chip (SoCs) being in most cases the dominant part in both area and power. Additionally, it determines the overall system's speed. As a result, new memory architectures and technologies have been developed over the years in order to improve the overall system performance. This project introduces the design and implementation of a memory controller algorithm that increases the throughput while guaranteeing a fix access-rate of the memory. The work is focused on incrementing the number of read operations, i.e., being capable of performing two-read operation per clock cycle, with the use of single-port memory banks. Three different algorithms are implemented (XOR solution, Word Addition solution (WA), and Bit Addition solution (BA)) and are compared in terms of area, power and speed. Moreover, they are compared to the conventional two-port memory solution. In addition, a simple BIST (built-in self-test) engine has been implemented in order to perform a basic functionality test in memory. The BIST module is integrated into the Word Addition solution. The project concludes that the area per bit of the three solutions decreases as the size of the memory increases. However, it is by increasing the number of rows that the lowest cell area per bit values are achieved. The three solutions reduce the power and the area compared to the conventional two-port memory solution, with the XOR solution being the most area and power efficient. Even though the area and power increase between solutions is significant, when considering the memory block system (memory controller and memory banks), the overall area and power difference is negligible. Moreover, the three solutions have shown to be able to work at higher speeds than conventional 28nm SRAM. Also, the system with the integrated BIST into the memory controller has an area and power significantly smaller compared to the conventional two-port memory solution. Finally, the memory controller speed is not affected by the BIST.

Cited by 0

Memory Controller for 1Gb LPDDR2 Memory Initialization Sequence

Jin-Su Kang, Chang-Yong Lee, Yong–Hwan Lee · The Journal of Korean Institute of Information Technology · 2022

각 메모리들은 정상 동작을 진행하기 전에 각자의 초기화 시퀀스가 존재한다. 이러한 시퀀스는 메모리가 오류 없는 정상 동작을 하기 위한 단계로서 필수적으로 진행되어야 한다. 본 논문에서는 1Gb LPDDR2(Low Power Double Data Rate)의 초기화 시퀀스를 자동으로 진행해 주는 메모리 컨트롤러의 시퀀스를 제안한다. 메모리의 초기화 시퀀스는 딜레이 타임 구간, 메모리 설정, 타이밍 조정 총 3단계로 나누어져 있다. 메모리 컨트롤러는 딜레이를 계산하고, 사용자의 설정에 맞추어 메모리의 초기 설정값을 조정하며 타이밍 조정을 위한 특정 패턴의 데이터를 쓰고 읽는다. 이러한 단계를 외부에서 진행하면 불필요한 시간 소모 및 정확한 운용이 어렵다. 본 논문에서 제안하는 메모리 컨트롤러를 사용하면 불필요한 시간 소모 없이 정확한 메모리 초기화 시퀀스의 진행이 가능하다.

Cited by 0

Adaptive Memory Controller for High-performance Multi-channel Memory

Jin-ku Kim, Jongbum Lim, Woo-cheol Cho et al. · JSTS Journal of Semiconductor Technology and Science · 2016

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

Cited by 1Open access

Security Support on Memory Controller for Heap Memory Safety

Chaochao Zhang, Rui Hou · 2022

Memory corruption attacks have existed for multiple decades, and have become a major threat to computer systems. At the same time, a number of defense techniques have been proposed by research community. With the wide adoption of CPU-based memory safety solutions, sophisticated attackers tend to tamper with system memory via direct memory access (DMA) attackers, which leverage DMA-enabled I/O peripherals to fully compromise system memory. The Input-Output Memory Management Units (IOMMUs) based solutions are widely believed to mitigate DMA attacks. However, recent works point out that attackers can bypass IOMMU-based protections by manipulating the DMA interfaces, which are particularly vulnerable to race conditions and other unsafe interactions.State-of-the-art hardware-supported memory protections rely on metadata to perform security checks on memory access. Consequently, the additional memory request for metadata results in significant performance degradation, which limited their feasibility in real world deployments. For quantitative analysis, we separate the total metadata access latency into DRAM latency, on-chip latency, and cache latency, and observe that the actual DRAM access is less than half of the total latency. To minimize metadata access latency, we propose EMC, a low-overhead heap memory safety solution that implements a tripwire based mechanism on the memory controller. In addition, by using memory controller as a natural gateway of various memory access data paths, EMC could provide comprehensive memory safety enforcement to all memory data paths from/to system physical memory. Our evaluation shows an 0.54% performance overhead on average for SPEC 2017 workloads.

Cited by 1

Memory Controller Design Under Cloud Workloads

Mahmoud, Mostafa, Moshovos, Andreas · arXiv (Cornell University) · 2016

This work studies the behavior of state-of-the-art memory controller designs when executing scale-out workloads. It considers memory scheduling techniques, memory page management policies, the number of memory channels, and the address mapping scheme used. Experimental measurements demonstrate: 1)~Several recently proposed memory scheduling policies are not a good match for these scale-out workloads. 2)~The relatively simple First-Ready-First-Come-First-Served (FR-FCFS) policy performs consistently better, and 3)~for most of the studied workloads, the even simpler First-Come-First-Served scheduling policy is within 1\% of FR-FCFS. 4)~Increasing the number of memory channels offers negligible performance benefits, e.g., performance improves by 1.7\% on average for 4-channels vs. 1-channel. 5)~77\%-90\% of DRAM rows activations are accessed only once before closure. These observation can guide future development and optimization of memory controllers for scale-out workloads.

Cited by 0Open access

Memory Controller KEY FEATURES GENERAL DESCRIPTION

Field Upgradeable · 2014

In order to offer the most compact and complete solutions to customers, intoPIX proposes companion IP-Cores that have been especially designed to ease the integration of our JPEG 2000 encoders and decoders into your platform, speeding up time-to-market. By completing your JPEG 2000 solutions with our companion IP-Cores, you will benefit from intoPIX’s know-how for all your solutions.

Cited by 0

Impulse: building a smarter memory controller

J. Carter, Wilson C. Hsieh, Leigh Stoller et al. · 1999

Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.

Cited by 232