Search 250 million research papers

UPC++ memory model.

Jorge González-Domínguez (843635), Yongchao Liu (310914), Bertil Schmidt (84784) · Figshare · 2016

Cited by 0Open access

Dynamic Memory Model

Susan Craw · Encyclopedia of Machine Learning · 2010

Cited by 0

HSA memory model

Benedict R. Gaster · 2013

Presents a collection of slides covering the following topics: heterogeneous system architecture; data structures; and modem memory model.

Cited by 7

Smart Memory: The Memory Processor Model

Tony Martinez Computer, Tony R. Martinez · 1990

This paper overviews and proposes a class of smart memory devices called the memory processor model. Smart memory entails the tight coupling of memory and logic. The model seeks to alleviate the von Neumann bottleneck, take advantage of technology trends, improve overall system speed, and add encapsulation advantages. Speed is increased through locality of processing, communication savings, higherlevel functionality, and parallelism. Parallelism is exploited at both the micro and macro levels. Data objects are accessed through descriptors, which give the memory a meta-knowledge concerning the objects, allowing for nontraditional access mechanisms. Both data types and operations are programmable. Innovative processing schemes, coupled with emerging technology densities, allow for substantial speed-up in traditional and novel memory operations. Three important paradigms introduced are descriptor processing, where operations are accomplished without access to the actual data, associative descriptor processing, supporting highly parallel access and processing, and the single-program multiple-data method, allowing parallelism by simultaneous processing of data objects distributed amongst multiple smart memories. Examples of specific operations are presented. This papers presents initial studies into the smart memory mechanism with the goal of describing its potential and stimulating further work

Cited by 0

Atomic Memory Model

M. Bonchev · Mathematics Computer Science and Education · 2024

Memory leaks and buffer overruns are among the most common erroneous conditions in computer systems. They are also among the most tedious, difficult and time consuming to detect, identify, locate, and resolve. Both Microsoft and Google independently report that memory safety issues cause 70% of all security vulnerabilities [10]. The Atomic Memory Model provides a mechanism for resolving these types of errors. Simultaneously, it makes the software architecture more robust and elegant by enforcing a code hierarchy regarding the memory use, as well as allowing for innate memory abstraction that matches the application semantics. The model also significantly increases the speed of the software development by relieving developers from detailed memory management.

Cited by 0Open access

OpenCL memory model.

Yupu Song (12501028), Cailin Li (17743113), Shiyang Xiao (17743116) et al. · Figshare · 2024

<div><p>In the process of Canny edge detection, a large number of high complexity calculations such as Gaussian filtering, gradient calculation, non-maximum suppression, and double threshold judgment need to be performed on the image, which takes up a lot of operation time, which is a great challenge to the real-time requirements of the algorithm. The traditional Canny edge detection technology mainly uses customized equipment such as DSP and FPGA, but it has some problems, such as long development cycle, difficult debugging, resource consumption, and so on. At the same time, the adopted CUDA platform has the problem of poor cross-platform. In order to solve this problem, a fine-grained parallel Canny edge detection method is proposed, which is optimized from three aspects: task partition, vector memory access, and NDRange optimization, and CPU-GPU collaborative parallelism is realized. At the same time, the parallel Canny edge detection methods based on multi-core CPU and CUDA architecture are designed. The experimental results show that OpenCL accelerated Canny edge detection algorithm (OCL_Canny) achieves 20.68 times acceleration ratio compared with CPU serial algorithm at 7452 × 8024 image resolution. At the image resolution of 3500 × 3500, the OCL_Canny algorithm achieves 3.96 times the acceleration ratio compared with the CPU multi-threaded Canny parallel algorithm. At 1024 × 1024 image resolution, the OCL_Canny algorithm achieves 1.21 times the acceleration ratio compared with the CUDA-based Canny parallel algorithm. The effectiveness and performance portability of the proposed Canny edge detection parallel algorithm are verified, and it provides a reference for the research of fast calculation of image big data.</p></div>

Cited by 0Open access

Memory Encoding Model

Huzheng Yang, James C. Gee, Jianbo Shi · arXiv (Cornell University) · 2023

We explore a new class of brain encoding model by adding memory-related information as input. Memory is an essential brain mechanism that works alongside visual stimuli. During a vision-memory cognitive task, we found the non-visual brain is largely predictable using previously seen images. Our Memory Encoding Model (Mem) won the Algonauts 2023 visual brain competition even without model ensemble (single model score 66.8, ensemble score 70.8). Our ensemble model without memory input (61.4) can also stand a 3rd place. Furthermore, we observe periodic delayed brain response correlated to 6th-7th prior image, and hippocampus also showed correlated activity timed with this periodicity. We conjuncture that the periodic replay could be related to memory mechanism to enhance the working memory.

Cited by 1Open access

HSA memory model

Gaster, B., Howes, L., Hower, D. · UWE Research Repository (UWE Bristol) · 2015

The HSA architecture has adopted a variant of the HRF-Relaxed memory model, which allows memory accesses to be controlled via fine grain scopes. This chapter introduces the HSA memory consistency model, how programmers can control memory visibility, and touches how programming languages like OpenCL and C++ can be represented.

Cited by 0

CLR Memory Model

Mohammad Ashiqur Rahman · Apress eBooks · 2014

As you have seen in Chapter 1, the CPU executes instruction by fetching it from the physical memory (RAM). The application code must reside somewhere in the physical memory to be executed by the CPU. It is therefore important that you manage the physical memory while the CPU executes an application. The OS plays a significant role in managing physical memory by abstracting it into a concept called virtual memory. The concept of the virtual memory gives the illusion to the user application that it has a huge range of memory to consume. The OS offers memory management services via the memory API.

Cited by 1

Hierarchical model of memory and memory loss

Jeffrey P. Sutton, J.S. Beis, L. E. H. Trainor · Journal of Physics A Mathematical and General · 1988

A neural circuit model is presented that consists of a hierarchy of nested clusters of neuron-like elements. Each hierarchical level of cluster organisation encodes a different level of distributed memory. Associate memory properties within and between levels are investigated numerically in simple versions of the model. The results may provide insight into mechanisms of memory storage, recall and loss in real neural circuits, such as those found in the cerebral cortex.

Cited by 32

Java Memory Model-Aware Model Checking

Huafeng Jin, Tuba Yavuz-Kahveci, Beverly A. Sanders · Lecture notes in computer science · 2012

Cited by 15

The CompCert memory model

Andrew W. Appel, Robert Dockins, Aquinas Hobor et al. · Cambridge University Press eBooks · 2014

The imperative programming paradigm views programs as sequences of commands that update a memory state. A memory model specifies memory states and operations such as reads and writes. Such a memory model is a prerequisite to giving formal semantics to imperative programming languages, verifying properties of programs, and proving the correctness of program transformations.

Cited by 6

A model for memory

S Sivakami, V. Srinivasan · Journal of Theoretical Biology · 1983

Cited by 20

An algebraic memory model

J. P. Moskowitz, C. Jousselin · ACM SIGARCH Computer Architecture News · 1989

Memory in the von Neumann computer is usually viewed as a linear array. We prove that this view does not follow from the consecutive nature of this memory, but from the group structure of the law performed in the address arithmetic unit. By changing that law, we can get a memory with a non commutative access. As an example we describe the metacyclic memory.

Cited by 5Open access

GPU memory model overview

Aaron Lefohn · 2005

Article Share on GPU memory model overview Author: Aaron Lefohn University of California, Davis University of California, DavisView Profile Authors Info & Claims SIGGRAPH '05: ACM SIGGRAPH 2005 CoursesJuly 2005 Pages 127–eshttps://doi.org/10.1145/1198555.1198775Online:31 July 2005Publication History 3citation1,080DownloadsMetricsTotal Citations3Total Downloads1,080Last 12 Months18Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Cited by 5

Resilient Weak Memory Model

Zhang, Sizhuo · DSpace@MIT (Massachusetts Institute of Technology) · 2016

Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.

Cited by 0Open access

Chaos associative memory model

Masahiro Nakagawa · 2003

In this paper we propose a chaos dynamic memory model applied to a chaotic autoassociation memory. The present artificial neuron model is properly characterized in terms of a time-dependent sinusoidal activation function to involve transient chaotic dynamics as well as the energy steepest descent strategy. It is shown that the present neural network has a remarkable retrieval ability beyond that of conventional models with such a monotonous activation function as a sigmoidal one. This advantage is found to result from the analogue periodic mapping accompanied by the chaotic behaviour of the neurons as well as the symmetry of the dynamic equation.

Cited by 0

Thermodynamic model for memory

Qinyi Zhao · Biosystems · 2024

A thermodynamic model for memory formation is proposed. Key points include: 1) Any thought or consciousness corresponds to a thermodynamic system of nerve cells. 2) The system concept of nerve cells can only be described by thermodynamics of condensed matter. 3) The memory structure is logically associated with the system structure or the normal structure of biology. 4) The development of our thoughts is processed irreversibly, and numerous states or thoughts can be generated. 5) Memory formation results from the reorganization and change of cellular structures (or memory structures), which are related to nerve cell skeleton and membrane. Their alteration can change the excitability of nerve cells and the pathway of neural impulse conduction. 6) Amnesia results from the loss of thermodynamic stability of the memory structure, which can be achieved by different ways. Some related phenomena and facts are discussed. The analysis shows that thermodynamics can account for the basic properties of memory.

Cited by 4Open access

The memory transfer model.

Alex Roxin (272198), Stefano Fusi (437589) · Figshare · 2015

<p><b>a.</b> Upper left: In the model, the state of each synapse in stage one is updated stochastically in response to the occurrence of plasticity events. The synapses of downstream stages update their state according to the state of upstream stages. Lower left: Memories are encoded by subjecting the synapses in stage 1 of stages to a pattern of plasticity events, here illustrated by different colors. The correlation of synaptic states with a memory is initially zero in downstream stages, and builds up over time through feed-forward interactions. Right: The consolidation model always outperforms the heterogeneous model without interactions at sufficiently long times. Here a two-stage model is illustrated. The dashed line is the SNR of the second stage in the heterogeneous model. See text for details. <b>b.</b> The memory wave: the memory trace (from <a href="http://www.ploscompbiol.org/article/info:doi/10.1371/journal.pcbi.1003146#pcbi.1003146.e320" target="_blank">Eq. 1</a>) in the consolidation model travels as a localized pulse from stage to stage (starting from , in fast learning stages, presumably localized in the medial temporal lobe, and ending at , in slow learning stages). Here and . Stage has a learning rate and . New memories are encoded at a rate of one per hour.</p>

Cited by 0Open access

Memory Model and Atomics

James Reinders, Ben Ashbaugh, James Brodman et al. · Apress eBooks · 2020

Abstract Memory consistency is not an esoteric concept if we want to be good parallel programmers. It is a critical piece of our puzzle, helping us to ensure that data is where we need it when we need it and that its values are what we are expecting. This chapter brings to light key things we need to master in order to ensure our program hums along correctly. This topic is not unique to SYCL or to DPC++.

Cited by 0Open access