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About 10,000 papers for “Network processor”

Network Access Processor

2008

Dissemination or disclosure of this proprietary and confidential information is NOT permitted without the written consent of Cavium Networks.

Cited by 0

The network processor decision

Michael Coss, Ron Sharp · Bell Labs Technical Journal · 2004

Since the introduction of network processors about four years ago, product developers have been pondering the question of whether they should adopt this exciting new technology. This paper will help these developers determine if network processors are appropriate for their application. However, deciding to use network processors is only the first step. The second and more difficult step is deciding which network processor to use. The roughly 30 network processors on the market today vary greatly in architecture, features, and performance. This paper will describe the basic differences among network processors and attempt to look past much of the hyperbole that surrounds them. The information and opinions expressed in this paper derive from the authors' experiences building platforms using network processors for Lucent Technologies. A brief description of these platforms and the lessons learned from them is included in this paper.

Cited by 6

Network Processor Performance Evaluation Framework

Zheng Shan, Rongcai Zhao, Xie Kang-min · 2006

Computer networks provide an increasing number of services that require complex processing of packets, for example firewalls, load balancing, network storage, and TCP/IP offloading. Such services require the use of powerful network processors to provide the necessary performance and flexibility. But NPs also introduce new challenges. It is important to study the performance of NP system so that one can take full advantage of NP resources to achieve the required performance for a given application. It is therefore desirable to develop a framework for analyzing performance of NP-based applications. The framework divides the network processor system into four levels, and incorporates Petri net, AD AG and a new analysis method- "line space" to evaluate NP-based system performance, which simplifies the complexity of multilevel parallel system performance evaluation and insures its efficiency and precision. We apply our methodology to an Intel's reference design, and show that the analytical results using our method match the experimental results from actual implementation.

Cited by 2

A Network Multi-Processor for . . .

T. A. Marsland, T. Breitkreutz, S. Sutphen · 1991

Although both shared memory and loosely coupled parallel computing systems are now common, many still do not offer an easy way to design, implement, and test parallel algorithms. Our system provides software tools that make possible a variety of connection structures between processes. These structures are said to form a `Network MultiProcessor', which is implemented on a local area network of heterogeneous UNIX-based timesharing computers, plus a set of processor boards dedicated to an application so that accurate timing measurements can be made. We explain how these tools have been used both to aid parallel algorithm development and to explore the properties of different computer interconnection methods.

Cited by 0

NMP - A Network Multi-Processor

T.A. Marsland, Steven F. Sutphen, T. Breitkreutz · University of Alberta Library · 1988

The report describes an environment for performing experiments in distributed processing. It replaces an earlier (1985) report, reflecting changes in the system and terminology. Our system offers researchers an easy way to design, implement, and test parallel algorithms. It provides software tools which make possible a variety of connection structures between processes. These process structures are said to form a Network Multiprocessor (implemented on a local area network of VAX 11/780’s, Sun workstations, dedicated MC68000 processor boards, and a MIPS M/1000). We show how these tools have been used both to aid parallel algorithm development and to explore different computer interconnection methods.

Cited by 4Open access

Aggregation of Network Processor Compiler

Zhang Zhaoqing · 2007

This paper describes a heterogeneous multi-processor complier Shangri-la which constitutes a uniform compiler back-end based on whirl2c.By address translation it resolves the problem of pointer sharing arose by different access memory methods.By these techniques Shangri-la integrates two kinds of processors to work on the same compiler.This uniform compile platform sets programmers free from traditional fussy network programming.

Cited by 0

Taming the IXP network processor

Lal George, M. Blume · 2003

We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal bank assignment, and spills. The compiler's optimizer employs CPS as its intermediate representation; some of the invariants that this IR guarantees are essential for the formulation of a practical ILP model.Appel and George used a similar ILP-based technique for the IA32 to decide which variables reside in registers but deferred the actual assignment of colors to a later phase. We demonstrate how to carry over their idea to an architecture with many more banks, register aggregates, variables with multiple simultaneous register assignments, and, very importantly, one where bank- and register-assignment cannot be done in isolation from each other. Our approach performs well in practise---without causing an explosion in size or solve time of the generated integer linear programs.

Cited by 37

Array processor architecture connection network

Shafer, Philip E., Barnes, George H., Lundstrom, Stephen F. · NASA Technical Reports Server (NASA)

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Cited by 0Open access

IXP2400 network processor package development

A. Janian, A. Hasan, U. Sheth et al. · 2004

This paper describes the application and performance of network processors (NPU) and the development of packaging for the new IXP2400 NPUs. Flip chip interconnect packaging, applied first time to Intel NPUs, is described. The package used for very high I/O and ball count with a 1.0 mm pitch fully populated BGA is a first in its class. The details of the package substrate design are described and the package substrate characteristics along with validation are discussed. High ambient temperature for certain applications was specially challenging for cooling solutions. The techniques applied to circumvent packaging problems are described in the paper which include alignment of the package with the market demand and reconciling the silicon reliability for such solutions. The issues related to solder joint reliability for a 1.0 mm pitch BGA and its interactions with board level enabling are discussed with methods considered to improve it. Finally, the future direction of NPU products and the demands on packaging are listed.

Cited by 4

The APP300 access network processor

Balakrishnan Sundararaman · 2006

This article consists of a collection of slides from the author's conference presentation on Agere's APP300 Access Network Processor. Some of the specific topics discussed include: targeted markets for the processor line; data communications capabilities of the APP300 processor; the company approach to marketing the product line; APP300 block diagram; unified memory architecture; classifier and policing engines, features versus benefits; traffic management capabilities; scheduling hierarchies; and processing subsystems.

Cited by 0

Deep Neural Network Inference Processor

Ali Hegazy, Khaled Salah · 2023

In recent years, neural networks’ architecture has become complicated and it demands special computing requirements. Thus, new specialized microprocessors are proposed for this purpose. In this paper, a new scalable neural network inference processor architecture is proposed and implemented on FPGA. FPGA enables hardware customization to fit the specific computing requirements. Moreover, FPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. In the proposed FPGA-based architecture, the size of the systolic matrix multiplication array, the size of data flowing inside the processor and all the primitive blocks of the processor are configurable and scalable. Also, in this paper, an illustrative example is introduced to show how a TensorFlow-Based neural network model can be inferred using the proposed architecture. Moreover, synthesis results in terms of area and power are very promising. The design is validated on Virtex UltraScale+ VCUIIS Evaluation platform. It is tested using face recognition algorithm (160×160 face image at 25FPS) where it achieved an accuracy of 95%. Moreover, it shows performance and power efficiency of 55 GOPS and 10 GOPS/W at 100MHz, respectively.

Cited by 0