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About 6,056 papers for “Networking hardware”

Hardware and Networking

Vikhyath Bangera · Zenodo (CERN European Organization for Nuclear Research) · 2022

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Cited by 0Open access

Hardware Support for Active Networking

Ros G. Fragkiadakis, Nikolaos G. Bartzoudis, David J. Parish et al. · 2003

A new reconfigurable active router architecture is presented in this paper. It consists of a software part and a hardware part. The software part is a set of kernelspace and user-space modules running on linux-PC. An FPGA PCI-based board with a Virtex-1600E FPGA forms the hardware part. The integration of reconfigurable hardware into standard PC hardware allows for on-the-fly reconfigurable hardware.

Cited by 0

Seamless Hardware-Accelerated Kubernetes Networking

Mircea M. Iordache-Sica, Tula Kraiser, Olufemi Komolafe · 2023

Kubernetes has quickly become the industry-standard Service management and orchestration framework. However, Kubernetes networking has traditionally been achieved by software implementations of CNI (Container Networking Interface) plugins with performance limitations. This paper puts forward the integration of hardware networking appliances for enhancing Kubernetes performance in Data Center environments by utilising the Hardware Accelerated Kubernetes (HAcK) architecture. The proposed architecture is applied to the implementation of the HAcK LoadBalancer which leverages industry-grade network appliances for creating unified application and infrastructure management mechanisms. Performance of the system is evaluated in real data centre scenarios.

Cited by 3

Reconfigurable Networking Hardware: A Classroom Tool

Martín Casado, Gregory R. Watson, Nick McKeown · 2006

We present an educational platform for teaching the design, debugging and deployment of real networking equipment in the operational Internet. The emphasis of our work is on teaching and, therefore, on providing an environment that is flexible, robust, low cost and easy to use. The platform is built around 'NetFPGAs'-custom boards containing eight Ethernet ports and two FPGAs. NetFPGA boards, when used with VNS (Virtual Network System-another tool we have developed), can be integrated into dynamically configurable network topologies reachable from the Internet. VNS enables a user-space process running on any remote computer to function as a system controller for the NetFPGA boards. NetFPGA and VNS are used at Stanford in a graduate level networking course to teach router implementation in hardware and software.

Cited by 11

Introduction to Computer Networking and Hardware Concepts

Nurul I. Sarkar · IGI Global eBooks · 2011

This chapter provides an introduction to computer networking and hardware concepts and highlights the use of software and hardware tools as an aid to enhance teaching and learning computer networking and hardware fundamentals. A basic knowledge of network topology, channel access protocol, network traffic, and networking devices is needed when designing and implementing a LAN. The term computer hardware refers to the physical components of a computer system — those that one can see and touch. The CPU, memory, and input and output devices are the main components of a computer. To understand the operation of a modern processor, it is important that the student grasp the basic concepts of computer hardware.

Cited by 0

Toward GPU-centric Networking on Commodity Hardware

Massimo Girondi, Mariano Scazzariello, Gerald Q. Maguire et al. · 2024

GPUs are emerging as the most popular accelerator for many applications, powering the core of machine learning applications. In networked GPU-accelerated applications input & output data typically traverse the CPU and the OS network stack multiple times, getting copied across the system's main memory. These transfers increase application latency and require expensive CPU cycles, reducing the system's efficiency, and increasing the overall response times. These inefficiencies become of greater importance in latency-bounded deployments, or with high throughput, where copy times could quickly inflate the response time of modern GPUs. We leverage the efficiency and kernel-bypass benefits of RDMA to transfer data in and out of GPUs without using any CPU cycles or synchronization. We demonstrate the ability of modern GPUs to saturate a 100-Gbps link, and evaluate the network processing time in the context of an inference serving application.

Cited by 4Open access

Hardware-Software Co-Design für Embedded Networking

Sikora, Axel · Opus-HSO (Offenburg University of Applied Sciences) · 2006

Der integrierte Entwurf von Systemen, die aus Hardware und Software bestehen, ist bereits seit Jahrzehnten Gegenstand von Forschung und Entwicklung. Allerdings stehen erst seit einigen wenigen Jahren Werkzeuge und Bauelemente zur Verfügung, die auch kleineren Hochschulen einen kostengünstigen Entwurf solcher gemischter Systeme erlauben. In etwa der gleichen Zeit ist die Verbreitung von vernetzten und verteilten Embedded Systemen in immensem Maße angestiegen. Dieser Beitrag erläutert an Hand von typischen Fallbeispielen, wie beide Bereiche sinnvoll und praxisorientiert miteinander verbunden werden können, um eine neue qualitative Stufe der Systementwicklung zu erreichen.

Cited by 0

Delay Tolerant Networking on embedded Linux hardware

Stefan Schmidt, Technische Universität Braunschweig, Prof Dr et al. · 2010

Ich versichere, die vorliegende Arbeit selbstständig und nur unter Benutzung der angegebenen Hilfsmittel angefertigt zu haben. Braunschweig, den 2010-08-16 iii Implementing and evaluating an IEEE 802.15.4 convergence layer for Delay Toler-ant Networking is the aim of this thesis. We discuss how we prepare the underlying Linux system, correct problems in the radio driver and implement the convergence layer between the ieee802154 Linux stack and IBR-DTN. Based on this implementa-tions we evaluate data throughput as well as packet loss and round trip time for either the raw IEEE 802.15.4 network or with the DTN layer on top. The potential bottle-necks revealed by the evaluation are discussed and future improvements are suggested. v

Cited by 0

A reconfigurable hardware networking platform for Smart Grid

Rami Amiri, Omar Elkeelany · 2012

Embedded system cores for communications networks are becoming much important recently due to the demands placed by Smart Grid, sensor mobile networks, etc. However, embedded system designs have unique metrics such as cost, flexibility, and size. Tuning these metrics during embedded system designs will definitely impact the cost and performance of Smart Grid devices and systems. In this research, we are aiming to achieve secure and high performance network communication platform based on various implementation of the TCP/IP protocol stack. Firstly, we deployed NicheStack TCP/IP for an embedded Web server application. Then, we integrated the ECC (Elliptic Curve Cryptography) C code within the web server source code to achieve a secure communication. Consequently, we showed that the integrated system: the web server, and the ECC program hides information if the secret is not provided. We used an http client to access the web server through the Internet. The client sends an encrypted data securely through the network to the embedded web server application. Secondly, we are in a stage to design a complete open TCP/IP hard core on an FPGA. Preliminary simulation result via ModelSim confirms proper operation of decode instruction module at the hardware level. All Modules will be synchronized to the same clock and reset signals.

Cited by 4

Applicability of Hardware-Supported Containers in Low-Latency Networking

Wiedner, Florian, Daichendt, Alexander, Andre, Jonas et al. · Technische Universität München, Universitätsbibliothek · 2025

Containers share the kernel with the host OS, which has implications for the network stack. Achieving connectivity between containers exclusively in software is unsuitable for reliable, low-latency applications. While extensive research has been conducted on virtual machines processing real-time traf- fic with hardware support, the impact of network latencies in containerized environments has received comparatively less attention. This paper analyzes throughput and network latencies in container topologies on a single host featuring single-root input/output virtualization, Linux Containers, and commercial off-the-shelf hardware. Using a state-of-the-art timestamping methodology, we measure latencies with a resolution of 1.25 µs without introducing delay by the measurement methodology itself. We evaluate a single flow in a line topology with up to 64 containers. The experiments demonstrate that pinning interrupt request handlers to non-uniform memory access nodes increases throughput and decreases latencies. Furthermore, we identify dTLB misses, rescheduling interrupts, and soft interrupt floods as critical challenges as they cause spikes in latencies, and isolation is impossible. This paper contributes findings to minimize bottlenecks and limitations for real-time container applications.This Dataset contains the Raw Data for a Line Topology and a Complex Topology.

Cited by 0Open access

Frame Shared Memory: Line-Rate Networking on Commodity Hardware

2014

Network processors provide an economical programmable platform to handle the high throughput and frame rates of modern and next-generation communication systems. However, these platforms have exchanged general-purpose capabilities for performance. This paper presents an alternative; a software frame-work for commodity general-purpose architectures ca-pable of high-rate and throughput sequential frame pro-cessing compatible with high-level languages and general-purpose operating system. A cache-optimized concur-rent lock free queue provides the low-overhead core-to-core communication necessary to sustain sequential frame processing rates beyond the 1.41 million frames per second realized on gigabit Ethernet while permit-ting per-frame processing time expansion with pipeline parallelism. 1.

Cited by 0

Applicability of Hardware-Supported Containers in Low-Latency Networking

Alexander Daichendt, Florian Wiedner, Jonas Andre et al. · 2024

Containers share the kernel with the host OS, which has implications for the network stack. Achieving connectivity between containers exclusively in software is unsuitable for reliable, low-latency applications. While extensive research has been conducted on virtual machines processing real-time traffic with hardware support, the impact of network latencies in containerized environments has received comparatively less attention. This paper analyzes throughput and network latencies in container topologies on a single host featuring single-root input/output virtualization, Linux Containers, and commercial off-the-shelf hardware. Using a state-of-the-art timestamping methodology, we measure latencies with a resolution of 1.25 μs without introducing delay by the measurement methodology itself. We evaluate a single flow in a line topology with up to 64 containers. The experiments demonstrate that pinning interrupt request handlers to non-uniform memory access nodes increases throughput and decreases latencies. Furthermore, we identify dTLB misses, rescheduling interrupts, and soft interrupt floods as critical challenges as they cause spikes in latencies, and isolation is impossible. This paper contributes findings to minimize bottlenecks and limitations for real-time container applications.

Cited by 1

Models for "Toward GPU-centric Networking on Commodity Hardware

Massimo Girondi · Zenodo (CERN European Organization for Nuclear Research) · 2024

Models and scripts to be used for the evaluation of "Toward GPU-centric Networking on Commodity Hardware". Original models are distributed under their original licenses.

Cited by 0Open access

Software and Hardware Techniques for Power-Efficient HPC Networking

Torsten Hoefler · Computing in Science & Engineering · 2010

Although most large-scale systems are designed with the network as a central component, the interconnection network's energy consumption has received little attention. However, several software and hardware approaches can increase the interconnection network's power efficiency by using the network more efficiently or using throttling bandwidths to reduce the power consumption of unneeded resources.

Cited by 20