Girish P. Ch, George Varghese · 1996
Abstract|In high speed networks, packet processing is relatively expensive while bandwidth is cheap. Thus it pays to add information to packet headers to make packet processing easier. While this is an old idea, we describe several speci c new mechanisms based on this principle. We describe a new technique, source hashing, which can provide O(1) lookup costs at the Data Link, Routing, and Transport layers. Source hashing is especially powerful when combined with the old idea of a ow ID; the ow identier allows packet processing information to be cached, and source hashing allows e cient cache lookups. Unlike Virtual Circuit Identi ers (VCIs), source hashing does not require a round trip delay for set up. In an experiment with the BSD Packet Filter implementation, we found that adding a ow ID and a source hash improved packet processing costs by a factor of 7. We also found a 45 % improvement when we conducted a similar experiment with IP packet forwarding. We also describe two other new techniques: threaded indices, which allows fast VCI-like lookups for datagram protocols like IP; and a Data Manipulation Layer, which compiles out all the information needed for Integrated Layer Processing and scheduling into an easily accessible portion of each packet. 1
Cited by 0
Girish Chandranmenon, George Varghese · IEEE/ACM Transactions on Networking · 1996
In high speed networks, packet processing is relatively expensive while bandwidth is cheap. Thus, it pays to add information to packet headers to make packet processing easier. While this is an old idea, we describe several specific new mechanisms based on this principle. We describe a new technique, source hashing, which can provide O(1) lookup costs at the data link, routing, and transport layers. Source hashing is especially powerful when combined with the old idea of a flow identifier (flow ID); the flow ID allows packet processing information to be cached and source hashing allows efficient cache lookups. Unlike virtual circuit identifiers (VCIs), source hashing does not require a round-trip delay for set up. In an experiment with the BSD packet filter implementation, we found that adding a flow ID and a source hash improved packet processing costs by a factor of seven. We also found a 45% improvement when we conducted a similar experiment with IP packet forwarding. We also describe two other new techniques: threaded indices, which allows fast VCI-like lookups for datagram protocols like IP; and a data manipulation layer (DML), which compiles out all the information needed for integrated layer processing (ILP) and scheduling into an easily accessible portion of each packet.
Cited by 61
Perry Robertson · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023
A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.
Cited by 0Open access
Plotěný, Ondřej · Brno University of Technology Digital Library (Brno University of Technology) · 2019
Cílem této magisterské práce je návrh a implementace síťové sondy pro sledování toků na 10GbE rozhraní. Text se zabývá přehledem GNU/Linux nástrojů využívaných ve vysokorychlostních sítích a principů jejich fungování. Dále pak je uveden návrh a implementace sondy využívající mechanismu zero-copy pro sledování provozu na 10GbE rozhraní. Aplikace využívá Expresní datové cesty (XDP) a jeho AF_XDP soketu pro zachycení provozu na rozhraní. Jako testovací platforma byla vybrána platforma NETX používaná na FIT VUT.
Cited by 0
Ramana Rao Kompella · 2012
No abstract available.
Cited by 0
Tom Barbette, Cyril Soldani, Laurent Mathy · DIAL (Catholic University of Leuven) · 2015
In recent years, we have witnessed the emergence of high speed packet I/O frameworks, bringing unprecedented network performance to userspace. Using the Click modular router, we rst review and quantitatively compare several such packet I/O frameworks, showing their superiority to kernel-based forwarding. We then reconsider the issue of software packet processing, in the context of modern commodity hardware with hardware multi-queues, multi-core processors and non-uniform memory access. Through a combination of existing techniques and improvements of our own, we derive modern general principles for the design of software packet processors. Our implementation of a fast packet processor framework, integrating a faster Click with both Netmap and DPDK, ex-hibits up-to about 2.3x speed-up compared to other software implementations, when used as an IP router.
Cited by 146Open access
Daly J, Bruschi V, Linguaglossa L et al. · IRIS Research product catalog (Sapienza University of Rome) · 2019
Cited by 0
Procházka, Aleš · Brno University of Technology Digital Library (Brno University of Technology) · 2019
Tato diplomová práce se věnuje filtrování a přeposílání paketů ve vysokorychlostních sítích. Nejdříve je představen framework DPDK, který je využíván pro rychlé zpracování paketů. Dále je popsán návrh aplikace pro vysokorychlostní filtrování paketů a návrh nástrojů pro usnadnění práce s touto aplikací. Následně je představena implementace tohoto návrhu a v neposlední řadě testování a srovnání výsledků se standardním firewallem
Cited by 0
Elo, Matias · Aaltodoc (Aalto University) · 2012
Software routing promises to offer more adaptive and easily programmable network nodes. Until now, however, it has been considered too inefficient for production environments in terms of both performance and cost. Several recent studies have shown that software routers are now capable of scaling up to the high-performance routing tasks even with commodity personal computer (PC) hardware. Network processors provide many of the same advantages as PC hardware including the ability of running selected custom software. In addition to this, they also provide hardware-accelerated circuits for packet processing related tasks. This thesis explores the possibility of running a modified PC software router on a network processing unit (NPU). The focus was to study if this approach provides any advantage over traditional off-the-shelf PC hardware with a comparable price point. This has been researched by modifying an open source routing application Click to run efficiently on Cavium Octeon network processors. The modified Click version avoids the bottlenecks, which traditionally hinder the performance of software routers. It utilizes Octeon hardware units to accelerate various packet processing tasks. The implementation also supports multithreading on Octeon processors, which greatly increases the performance. With the implemented modifications, a very high raw packet forwarding rate was achieved compared to the standard Click running on the same hardware. The performance numbers were comparable to similar class PC hardware while the power consumption of the Octeon devices was approximately one-fourth of the PC hardware's consumption.
Cited by 0
Qiaobin Fu · OpenBU (Boston University) · 2020
In today’s Internet, it is highly desirable to have fast and scalable software packet processing solutions for network applications that run on commodity hardware. The advent of cloud computing drives the continued rapid growth of Internet traffic. Moreover, the development of emerging networking techniques, such as Network Function Virtualization, significantly shapes the need for implementing the network functions in software. Finally, with the advancement of modern platforms as well as software frameworks for packet processing, network applications have potential to process 100+ Gbps network traffic on a single commodity server. Representative frameworks include the Click modular router, the RouteBricks scalable routing architecture, and BUFFALO, the software-based Ethernet switch. Beneath this general-purpose routing and switching functionality lie a broad set of network applications, many of which are handled with custom methods to provide cost-effectiveness and flexibility. This thesis considers two long-standing networking applications, IP lookup and distributed denial-of-service (DDoS) mitigation, and proposes efficient software-based methods drawing from this new perspective. \n \nIn this thesis, we first introduce several optimization techniques to accelerate network applications by taking advantage of modern CPU features. Then, we explore the IP lookup problem to find the longest matching prefix of an IP address in a set of prefixes. An ideal IP lookup algorithm should achieve small constant IP lookup time, and on-chip memory usage. However, no prior IP lookup algorithm achieves both requirements at the same time. We propose SAIL, a splitting approach to IP lookup, and a suite of algorithms for IP lookup based on SAIL framework. We conducted extensive experiments to evaluate our algorithms, and experimental results show that our SAIL algorithms are much faster than well-known IP lookup algorithms. Next, we switch our focus to DDoS, an attempt to disrupt the legitimate traffic of a victim by sending a flood of Internet traffic from different sources. Our solution is Gatekeeper, the first open-source and deployable DDoS mitigation system. We present a series of optimization techniques, including use of modern platforms, group prefetching, coroutines, and hashing, to accelerate Gatekeeper. Experimental results show that these optimization techniques significantly improve its performance over alternative baseline solutions.
Cited by 0
Robert Ennals Richard, Richard Sharp, Alan Mycroft · 2004
Cited by 0
2008
Increasing network speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP)[1][2] is the blanket name given to the processors, which are evolved with a tradeoff, flexibility Vs performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. Network Processors cover a spectrum of design tradeoff, that span in between the custom ASIC and the general-purpose processors. However the need is not yet well established and is undergoing continuous refinements. This paper focuses on the performance evaluation for network processors vis-à-vis general-purpose processors and determine if Network Processors have a role to play in design of network products in future.
Cited by 0
Feng Dong · 2002
With the fast progress of Internet, the backbone of Internet needs more powerful router with Gbps and even Tbps links. Thus, packet processing becomes the bottleneck of Internet backbone routers. Wire speed packet input processing is not only meaningful for Internet backbone router, but also useful in layer 4/7 switch, high speed firewall and intrusion detection system. In this paper, the recent advance in the research of wire speed packet input processing is survdyed, and the key problems and solutions of wire speed packet input processing are analyzed in detail. Finally, some open problems are identified.
Cited by 0
Robert Ennals, Richard R. Sharp, Alan Mycroft · 2004
Cited by 0
Harjot Gill, Dong Lin, Lohit Sarna et al. · 2012
As network applications become increasingly complex and heterogeneous, there is an increasing need for extensibility at the data plane, in order to carry out sophisticated functional-ities such as traffic flow management, filtering out unwanted
Cited by 0
Jingnan Yao, Laxmi N. Bhuyan · GLOBECOM '05. IEEE Global Telecommunications Conference, 2005. · 2005
In this paper, we propose a distributed packet processing algorithm on a peer-to-peer (P2P) network with the objective to minimize the total processing time. We consider an arbitrary P2P network comprising heterogeneous nodes interconnected via heterogeneous links. Each node on the network has its own local workload to be processed and is ready to share its extra processing power among other peer nodes upon request. We distribute the workload of a host to its peers by organizing them into an efficient resource tree. Since the key idea of this algorithm is to effectively share the available resources on the network by processing the load in a distributed manner, we refer to this approach as resource sharing distributed load processing (RSDLP) algorithm. We evaluate the performance with rigorous simulation experiments under generic system parameters.
Cited by 5
Benjamin Geib · MADOC (University of Mannheim) · 2012
Scalability is the key ingredient to further increase the performance of today’s supercomputers. As other approaches like frequency scaling reach their limits, parallelization is the only feasible way to further improve the performance. The time required for communication needs to be kept as small as possible to increase the scalability, in order to be able to further parallelize such systems. In the first part of this thesis ways to reduce the inflicted latency in packet based interconnection networks are analyzed and several new architectural solutions are proposed to solve these issues. These solutions have been tested and proven in a field programmable gate array (FPGA) environment. In addition, a hardware (HW) structure is presented that enables low latency packet processing for financial markets. The second part and the main contribution of this thesis is the newly designed crossbar architecture. It introduces a novel way to integrate the ability to multicast in a crossbar design. Furthermore, an efficient implementation of adaptive routing to reduce the congestion vulnerability in packet based interconnection networks is shown. The low latency of the design is demonstrated through simulation and its scalability is proven with synthesis results. The third part concentrates on the improvements and modifications made to EXTOLL, a high performance interconnection network specifically designed for low latency and high throughput applications. Contributions are modules enabling an efficient integration of multiple host interfaces as well as the integration of the on-chip interconnect. Additionally, some of the already existing functionality has been revised and improved to reach better performance and a lower latency. Micro-benchmark results are presented to underline the contribution of the made modifications.
Cited by 3Open access
Marco Canini, See Profile · 2013
All in-text\treferences\tunderlined\tin\tblue\tare\tlinked\tto\tpublications\ton\tResearchGate, letting you\taccess\tand\tread\tthem\timmediately.
Cited by 0
Oliver Hohlfeld, Helge Reelfs, Jan Rüth et al. · arXiv (Cornell University) · 2019
As network speed increases, servers struggle to serve all requests directed at them. This challenge is rooted in a partitioned data path where the split between the kernel space networking stack and user space applications induces overheads. To address this challenge, we propose Santa, a new architecture to optimize the data path by enabling server applications to partially offload packet processing to a generic rule processor. We exemplify Santa by showing how it can drastically accelerate kernel-based packet processing - a currently neglected domain. Our evaluation of a broad class of applications, namely DNS, Memcached, and HTTP, highlights that Santa can substantially improve the server performance by a factor of 5.5, 2.1, and 2.5, respectively.
Cited by 0Open access
G.B. Lockhart · 1988
The author explains the nature of packet communication networks, and discusses the reconstruction of lost packets at the receiver. Speech coding and packet protection are considered. >
Cited by 0