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About 6,839 papers for “Processor array”

Array Processor Architecture

Douglas J. Theis · Computer · 1981

Today's array processors provide a cost-effective tool for increasing the speed at which highly computation-bound processing jobs can be carried out. They are maturing and expanding with greatly improved hardware and software—improvements that are primarily a result of the accumulated experience of the vendors and users of these machines. All in all, it is a very competitive environment.

Cited by 9

Microcomputer Array Processor.

R. H. Ries, R. A. Hujar, F. C. Carty et al. · 1978

Abstract : The objective of this work was to design, fabricate, and bench test a feasibility model of an EW computer architecture based on utilizing multiple microprocessors in a multiprocessor system. The developed model consists of four microprocessors integrated into a tightly coupled nearly symmetrical structure exhibiting a master-slave relationship among its processors. Each microprocessor is composed of a 32-bit CPU and a dedicated local program memory. The function of the multiprocessor is to sort pulse trains based on digital pulse intercepts collected by a wide-open channelized receiver. Once the multiprocessor determines the PRI of an emitter, all emitter parameters are passed to a preprocessor which is inserted in the data stream between the receiver and the multiprocessor. The function of the preprocessor is to remove from the data stream all pulses from emitters identified by the multiprocessor. The feasibility model preprocessor can accept a peak receiver output pulse rate of 340,000 pulses per second.

Cited by 0

Spaceborne Processor Array

Whitaker, William D., Schatzel, Donald V., Chow, Edward T. et al. · NASA Technical Reports Server (NASA)

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Cited by 0Open access

Distributed array processor

Liddell, H, Social Science Research Council, London (United Kingdom) · OpenGrey (Institut de l'Information Scientifique et Technique) · 1983

Cited by 0

Flight array processor

NASA STI Repository (National Aeronautics and Space Administration)

Spaceflight applications for the NASA Scatterometer (NSCAT) , an ocean surface wind measuring system flown as part of the Navy Remote Ocean Sensing System (NROSS) are discussed in outline form, along with information on the Advanced Digital Synthetic aperture radar Processor (ADSP) that is being developed for ground-based processing of spacecraft Earth observations. Design considerations are listed. A block diagram of the scatterometer is given.

Cited by 0Open access

Array processor architecture

Lundstrom, Stephen F., Shafer, Philip E., Barnes, George H. · NASA Technical Reports Server (NASA)

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Cited by 0Open access

VLSI Array Processor

E. Greenwood · 1982

Abstract : Detail design of the Arithmetic Processor Unit (APU) chip has been completed. All cell types (100) have been run through the design rule check (DRC) programs, corrected and verified. DRC runs on the entire chip have been run and all corrections have been made. Fifteen out of eighteen of the chip DRC corrections have been verified. The metal, polysilicon and information data layers of the APU layout is shown. The attached drawings, titled 'VLSI Array Processor Arithmetic Processor Unit Chip Plan' is a detail drawing of the APU chip Plan. The functional level simulator of the APU has been built and verified using a set of APU diagnostic code. A gate level logic simulation of the APU has been built. The APU breadboard modules have been fabricated and check out has been initiated. The Array Processor Demonstration System (APDS) modules are in the wire-wrap process. The APDS and APU microcode assembler have been built and checked out. The linker and loader for the APDS have also been built.

Cited by 42

Array processor supercomputers

Jerry L. Potter, Will Meilander · Proceedings of the IEEE · 1989

The authors describe the range of hardware variations of array processors, a form of SIMD (simple instruction stream, multiple dates stream architecture), comparing and contrasting the significant differences among them and briefly illustrating the wide range of algorithms that can effectively utilize them. Three applications are reviewed. The first application, image convolution, represents the traditional numerically computationally intensive areas of application. SIMD array processors are sufficiently powerful to process digital imagery in real time easily. The second application, an example of real-time database management, is the air traffic control problem. The problem cannot be solved today by networks of computers that are successfully used in similar, less time-critical applications. With an array processor there is sufficient real time remaining after the present system tasks are accomplished to realize additional system enhancements. The third application area, graph algorithms, which is more theoretical, is representative of problems for which the simplicity of the array processor solution results in an execution time better than the best theoretical case for a conventional sequential implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 28

Berkeley Array Processor

Walthere Dere, D. Sakrison · IEEE Transactions on Computers · 1970

The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm, and others. This note describes the logical organization and performance of this device.

Cited by 2

Array processing on an array processor

David B. Erickson · 1975

Central memory is distributed across several processing elements on the ILLIAC-IV and similar array processors. This causes memory to appear two dimensional and raises special problems in the handling of arrays. Assignment of arrays to storage, and development of efficient array mapping functions and accessing techniques are all much more difficult than on conventional machines with “linear” memories. This paper discusses these problems as they relate to IVTRAN, a Fortran-like compiler for the ILLIAC-IV. Alternate solutions, useful in a different environment, are also explored.We shall start by giving a brief overview of the pertinent features of the ILLIAC-IV. The paper then describes IVTRAN constructs which may be used in expressing parallelism and the implications that these constructs have for array storage. Next, array mapping formulas are developed and the array packing problem is treated. Finally, argument passage and Fortran COMMON and EQUIVALENCE statements are discussed.

Cited by 2

The Microcode for the Control Processor of the ARO (Array Oriented Processor) Array Processor.

Heilbronn,D J · Defense Technical Information Center (DTIC) · 1983

A high speed array processor (ARO) has been designed for the processing of radar in real time. The operation of the ARO is supervised by a bit-slice microprocessor (the Control Processor). This document contains a description of the microcode which was written for the Control Processor to enable it to interpret PDP-11 assembler code. (Author)

Cited by 0

Optimum Adaptive Array Processor,

J. Chang, F. B. Tuteur · Defense Technical Information Center (DTIC) · 1967

This paper deals with the design and analysis of an adaptive array processor for use in passive detection of directional stochastic signals such as are found in sonar. The processor consists of a set of tapped delay-line filters, one for each array element. The algorithm used for adjusting the tap gains is a modification of the stochastic approximation method of Robbins and Monro, and it utilizes knowledge of the signal autocorrelation function and spatial direction of the target. It is shown that the final form approached by the processor is that of a space-time filter optimized in the direction corresponding to assumed target location. The system performance is analyzed by considering a noise field consisting of a spatially isotropic component and a single directional component referred to as an interference. It is shown that although the system initially cannot discriminate between the target and the interference, it eventually acts to eliminate the effect of the interference almost completely. It is also shown how the useful signal to noise ratio increases during adaptation. (Author)

Cited by 2

Acoustical Array Processor Design

Glen J. Culler, Michael McCammon · 1983

Abstract : This report describes the design of the acoustical array processor known as the CHI-5. The primary goal of the architecture was to provide hardware efficient, yet economical, in implementing linear predictive coding (LPC) algorithms for analysis and synthesis of speech. The CHI-5 can be used with a host processor or it can be used as a voice terminal in a stand alone data driven mode.

Cited by 0