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About 10,000 papers for “Processor design”

Processor Design

Espasa Sans, Roger, Canal Corretger, Ramon · Repositori UJI (Universitat Jaume I) · 2017

Cited by 0Open access

Processor Design

Espasa Sans, Roger, Canal Corretger, Ramon · QRU Quaderns de Recerca en Urbanisme · 2017

2017/2018

Cited by 0Open access

Embedded Processor Design

Xilinx Sp Board, Sp Bist (built-in Self Test, The Sp Microblaze · 2009

– The Built-In System Test (BIST) application uses an EDK MicroBlaze system to verify board functionality. A UART based terminal program interface offers users a menu of tests to run. � Reference Design IP – EDK IP: MicroBlaze, plb_v46, lmb_v10, mdm, lmb_bram_if_cntlr, bram_block, xps_bram_if_cntlr, xps_uart16550, xps_gpio, clock_generator,

Cited by 0

Chapter 3 Processor Design

2008

Processors come in many types and with many intended uses. While most attention is focused on high performance processors used in servers and workstations, by actual count these are a small percentage of processors produced in any year. Figure 3.1 is an estimate of the processor production profile by annual production count (NOT by

Cited by 0

Acoustical Array Processor Design

Glen J. Culler, Michael McCammon · 1983

Abstract : This report describes the design of the acoustical array processor known as the CHI-5. The primary goal of the architecture was to provide hardware efficient, yet economical, in implementing linear predictive coding (LPC) algorithms for analysis and synthesis of speech. The CHI-5 can be used with a host processor or it can be used as a voice terminal in a stand alone data driven mode.

Cited by 0

Verification-Aware Processor Design

Anita Lungu · DukeSpace (Duke University) · 2009

<p>As technological advances enable computers to permeate many of our society's critical application domains (such as medicine, finances, transportation), the requirement for computers to always behave correctly becomes critical as well. Currently, ensuring that processor designs are correct represents a major challenge for the computing industry consuming the majority (up to 70%) of the resources allocated for the creation of a new processor. Looking towards the future, we see that with each new processor generation, even more transistors fit on the same chip area and more complex designs become possible, which makes it unlikely that the difficulty of the design verification problem will decrease by itself.</p><p>We believe that the difficulty of the design verification problem is compounded by the current processor design flow. In most design cycles, a design's verifiability is not explicitly considered at an early stage - when decisions are most influential - because that initial focus is exclusively on improving the design on more traditional metrics like performance, power, and area. It is thus possible for the resulting design to be very difficult to verify in the end, specifically because its verifiability was not ranked high on the priority list in the beginning. </p><p>In this thesis we propose to view verifiability as a critical design constraint to be considered, together with other established metrics, like performance and power, from the initial stages of design. Our high level goal is for this approach to make designs more verifiable, which would both decrease the resources invested in the verification step and lead to more robust designs. </p><p>More specifically, we make five main contributions in this thesis. The first is our proposal for a change in design perspective towards considering verifiability as a first class constraint. Second, we use formal verification (through a combination of theorem proving, model checking, and probabilistic model checking ) to quantitatively evaluate the impact on verifiability of various design choices like the organization of caches, TLBs, pipeline, operand bypass network, and dynamic power management mechanisms. Our third contribution is to evaluate design trade-offs between verifiability and other established metrics, like performance and power, in the context of multi-core dynamic power management schemes. Fourth, we re-design several components for increasing their verifiability. Finally, we propose design guidelines for increasing verifiability. In the context of single core processors our guidelines refer to the organization of caches and translation lookaside buffers (TLBs), the depth of the core's pipeline, the type of ALUs used, while for multi-core processors we refer to dynamic power management schemes (DPMs) for power capping. </p><p>Our results confirm that making design choices with verifiability as a first class design constraint has the capacity to decrease the verification effort. Furthermore, making explicit trade-offs between verifiability, performance and power helps identify better design points for given verification, performance, and power goals.</p>

Cited by 0Open access

A display processor design

R. Watson, T. H. Myer, Ivan E. Sutherland et al. · 1969

This paper describes the results of a collaborative design effort aimed at development of a general purpose display system for the SDS-940 time-shared computer. The important features of the system evolved gradually from a number of separate design goals. We wanted a display system that would:

Cited by 4Open access

Super-scalar processor design

William M. Johnson · 1989

A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one instruction per clock cycle. Maintaining this execution rate is primarily a problem of scheduling processor resources (such as functional units) for high A number of scheduling algorithms have been published, with wide-ranging claims of performance over the single-instruction issue of a scalar processor. However, a number of these claims are based on idealizations or on special-purpose applications. This study uses trace-driven simulation to evaluate many different super-scalar hardware organizations. Super-scalar performance is limited caused by both branch delays and instruction mis b instruction-fetch inefficiencies of this instruction-fetch lirnitation, it is not worthwhile to explore highly-concurrent execution hardware, Rather, it is more appro to explore economical execution hardware that more closely matches the oughput provided b reducing the instruction-fetch inef the instruction This stud ciencies and explores the resulting examines techniques for ardware This study concludes that a super-scalar processor can have nearly twice the scalar processor, but that this re uires that four major hardware features: xformance of a out-o -order execution, register renarmng, branch pre and a four-instruction decoder. These features are interdependent, and removing any single feature reduces average performance by 18% or more. However, there are many hardware simplifications that cause only a small performance reduction.

Cited by 46

Parallel Processor Configuration Design

With Processing Transmission, Saravut Charcranoon, Thomas G. Robertazzi et al. · 2000

this paper, we examine a computer configuration design problem that has implications for the leasing of networked computer time

Cited by 0

Soft-core processor design

Franjo Plavec · TSpace · 2004

The Nios soft-core processor from Altera Corporation is studied and a Verilog implementation of the Nios soft-core processor has been developed, called UT Nios. The UT Nios is described, its performance dependence on various architectural parameters is investigated and then compared to the original implementation from Altera. Experiments show that the performance of different types of applications varies significantly depending on the architectural parameters. The performance comparison shows that UT Nios achieves performance comparable to the original implementation. Finally, the design methodology, experiences from the design process and issues encountered are discussed. Recent advancements in Field Programmable Gate Array (FPGA) technology have resulted in FPGA devices that support the implementation of a complete computer system on a single FPGA chip. A soft-core processor is a central component of such a system. A soft-core processor is a microprocessor defined in software, which can be synthesized in programmable hardware, such as FPGAs.

Cited by 0Open access

Parameterized Processor Design Suite

Navid Azizi, Borys Bradel, Tomasz Czajkowski et al. · 2001

This document describes the design of a Parameterized Processor Design Suite. Processors are traditionally implemented on Application Specific Integrated Circuit (ASIC) chips. Designing a processor on an ASIC chip is usually very costly and time consuming. As a result, programmable logic chips have been used as an alternative processor platform. These chips allow users to change their designs without incurring the manufacturing costs and delays involved in ASIC design. Programmable logic chips, however, require the user to know a Hardware Description Language (HDL) to be able to program them. Our project removes this need while retaining the benefits of using programmable logic chips. Our software suite allows a user to easily generate custom processors based on their needs without knowing an HDL. The software suite is a collection of three programs, a Graphical User Interface (GUI), a Hardware Generation Program (HGP), and an assembler. The GUI allows a user to specify the processor parameters. The GUI passes on the information that it received from the user to the HGP. The HGP uses this information to identify all of the hardware resources that the processor will need, all of the signals that will be transmitted between these resources, and a set of instructions that the processor will implement. Once the identification is complete, the HGP generates a set of HDL files that describe the processor. These HDL files are based on a set of hardware templates that are a major portion of this design project. These templates dictate the underlying structure of the processor. The HGP also passes on its information to the assembler. The assembler can take this information from the HGP and create machine-readable code from a user's source code. Several processors that have been ...

Cited by 0