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About 2,507 papers for “Programmable logic array”

Programmable logic machine (A programmable cell array)

Z.E. Skokan · IEEE Journal of Solid-State Circuits · 1983

The PLM is a single mask, programmable cell array with complete interconnect. It is 100% wireable and 100% testable with built-in LSSD, it achieves subnanosecond cell delay and 400-gate complexity with less than 1 W of power, and it is fabricated through a low-density process resulting in low cost and a four-day turnaround. This paper describes why the PLM was developed, its operational characteristics, and how it differs from conventional gate arrays.

Cited by 0

Memristor based programmable threshold logic array

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri et al. · 2010

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

Cited by 43Open access

Electrically alterable programmable logic array (EAPLA)

Yenyu Hsieh, R.J.K. Wood, P.P. Wang · 1980

A functional Electrically Alterable Programmable Logic Array (EAPLA) has been developed to serve as fast turn-around-time engineering hardware for custom structured macro design in VLSI. A novel electrically alterable, floating gate memory device has been developed with double polysilicon technology. It was used in the PLA array such that the personalization patterns of the PLA can be electrically altered in the users' laboratory after packaging. The non-volatile memory device employs channel hot electron injection to write and junction avalanche breakdown hot hole injection or Fowler-Nordheim electron tunneling across the oxides to erase. Unique features of the cell structures and implementation to the EAPLA will be discussed.

Cited by 2

S-SEED based programmable logic array

M. W. Derstine, W. R. Babbitt, John Bell et al. · Optical Society of America Annual Meeting · 1991

A promising candidate for logic arrays in optical cellular logic image processors is the symmetric self-electrooptic effect device (S-SEED). We describe the operation of an 8 × 16 array of S-SEEDs as programmable logic gates operating using the time sequential scheme described by Lentine et al. 1 with a space multiplexed beam combination technique. 2 The programmable gate operates at an effective rate >10 kHz which is limited by the speed of the computer drive, and >80% of the gates operate correctly simultaneously. The beam combination scheme used in this system requires that several different image planes be focussed onto the SEED array.

Cited by 0

Abstract CMOS Analog Programmable Logic Array

2008

In this paper, we present a methodology to design analog circuits and program the circuits using a digital bit stream to function like a desired complex circuit (ex. OTAs). The basic CMOS analog cells are synthesized from high-level circuit specifications into transistor net-lists using a two phase tuning process. The first phase uses a fast analog performance estimator to perform a global circuit sizing and the second phase involves Spice circuit simulations for a detail circuit sizing achieving high accuracy results. The synthesis environment relies on a genetic algorithm based heuristic method to search for a solution in a large designspace. 1

Cited by 0

Programmable Logic Array in Quantum Computing

Fatema Akter, Tamanna Tabassum, Mohammed Nasir Uddin · Lecture notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering · 2023

Cited by 1

Compact free-space optical programmable logic array

Yao Li, Andrew A. Kostrzewski, Dai Hyun Kim et al. · Annual Meeting Optical Society of America · 1988

To implement a parallel optical digital computer, in addition to the two variables, multiple variable optical logic gates are needed. One way to implement a generalized multiple variable optical logic device is to use an optical programmable logic array. We propose a new method to realize a medium scale, compact, and free-space optical programmable logic array. Using either a 2-D or an array of 1-D optical spatial light modulators inside a lens-based multiple-beam path cavity, an array of optical multiple variable logic product (AND gate) term is generated. This device, together with a programmable multiple variable logic OR matrix, can be used to implement any Boolean combinatorial logic operations. For an optical binary combinatorial logic computation, the proposed methods efficiently use 3-D space and optical elements. Preliminary experimental results obtained using an inexpensive liquid-crystal TV are included.

Cited by 0

Fault‐tolerant programmable logic array for nanoelectronics

Jacek Flak, Mika Laiho · International Journal of Circuit Theory and Applications · 2012

SUMMARY This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single‐electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright © 2012 John Wiley & Sons, Ltd.

Cited by 7

Development of Programmable Logic Array for Multiple-Valued Logic Functions

Vitaly Levashenko, Igor Lukyanchuk, Elena Zaitseva et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2020

The binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing multiple-valued logic (MVL) cells as computing and memory units reduces energy losses and enables to pack of unprecedented high-density information, but the current silicon-based material technologies have been studied marginally for the material realization of MVL devices. Here, we propose to use the ferroelectrics for the implementation of MVL units using their ability to pin the polarization as a sequence of multistable states. More specifically, the realization of a programmable logic array (PLA) based on MVL units is considered with the application of the ferroelectrics technology in implementation of memory units. The specific of the PLA construction is the use of generalized Reed-Muller expression for the representation of an MVL function. In this article, several possible implementations of such PLAs are considered, and their properties are analyzed from the logic design point of view.

Cited by 13

Design of a Ferroelectric Programmable Logic Gate Array

Todd C. Macleod, Fat D. Ho · Integrated ferroelectrics · 2003

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFETs in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The devices were only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The designs consist of a small array of logic gates. Other gates could easily be produced. They are linked by FFETs that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Cited by 6

82S100 Bipolar Field-Programmable Logic Array (FPLA) - datasheet

Signetics · Bulletin of Miscellaneous Information (Royal Gardens Kew) · 1975

Bipolar Programmable Logic Array containing 48 Product terms (AND terms) and 8 output functions. The true state of output functions is determined by an output Sum (OR) matrix by a logical combination of 16-input variables (or complements), up to 48 terms.

Cited by 0

Modified programmable logic array with more product terms

Lawrence A. Bennett · Electronics Letters · 1977

Some simple modifications to the basic programmable logicarray structure are described which result in an increase in the number of product terms available. Provided the degree of modification is small, then a worthwhile increase in the number of product terms is obtained with little disadvantage.

Cited by 0

High-speed static programmable logic array in LOCMOS

P. May, F.C. Schiereck · IEEE Journal of Solid-State Circuits · 1976

A large static programmable logic array (PLA) with 20 inputs, 94 product terms, and 24 outputs, designed and realized in LOCMOS, the complementary MOS technology with isolation by local oxidation of silicon. Layout and physical parameters of this technology resulted in a simple, dense, and low-capacity design. The dc and transient features of different realization possibilities have been simulated. Design automation tools have been developed to ensure error-free personalization of the PLA. A density of 160 gates per mm/SUP 2/ has been achieved. Samples show average propagation delays of 100 ns, while dissipation is typically 120 mW.

Cited by 1