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About 259 papers for “Reduced instruction set computing”
Vojin G. Oklobdzija · Wiley Encyclopedia of Computer Science and Engineering · 2007
Abstract Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline.
Cited by 3
Klaus Mølmer, Anders Søndberg Sørensen · 2000
Cited by 0
Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan et al. · IEEE Micro · 2014
This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete instruction can mirror any other instruction's semantics. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. The scope of using such an instruction is far greater than that of instructional purposes, and thus, the authors present its applicability to fault tolerance. In particular, they extend a million-instructions-per-second (MIPS) processor with the ultra-reduced instruction set coprocessor (URISC), which implements the subleq instruction. They use the URISC to execute sequences of subleq to mimic the semantics of instructions that are known to be faulty on the MIPS core after testing. The LLVM compiler back end generates the sequence of subleq for instructions marked as faulty. This presents a hardware-software approach to fault recovery. The authors experimentally evaluate the impact of single-upset faults on the instructions that are rendered faulty, the area overhead of the URISC, and the performance overhead of using the URISC.
Cited by 8
R Cascio · PubMed · 1994
Cited by 0
Jin Stone, Qiaodan (Qiaodan Jordan) · DSpace@MIT (Massachusetts Institute of Technology) · 2014
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cited by 0Open access
James T. Hunt · The Physics Teacher · 1987
First Page
Cited by 0
Joaquín Gracia-Morán, J.-Carlos Baraza-Calvo, Daniel Gil-Tomás et al. · IEEE Transactions on Reliability · 2014
With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.
Cited by 21Open access
Huaquipaco Encinas, Saul, Contreras Mamani, Richard John · renati · 2016
La automatización de las viviendas proponen mejorar cuatro aspectos fundamentales de las mismas, la seguridad, el ahorro energético, la accesibilidad y el confort; nosotros hemos puesto principal importancia en la seguridad y el ahorro energético. En la actualidad existen una gran variedad de sistemas y tecnologías disponibles que pueden ser utilizados y permiten obtener las prestaciones antes mencionadas tales como: HEYU, HCS, ExDomus, X10, etc. Sin embargo, se decidió trabajar con la tecnología web, teniendo como base del hardware del servidor un computador con arquitectura Reduced instruction Set Computing y como software de este un servidor LAMP. El sistema consta de actuadores y sensores que se comunican con el servidor a través de una tarjeta de control utilizando la tipología centraliza y la topología de red estrella que hacen que el servidor reciba toda la información proveniente de los sensores para que este las procese y envíe las ordenes correspondientes a los actuadores. Se hicieron análisis comparativos en cuanto al consumo energético de nuestro servidor con respecto a servidores tradicionales logrando obtener resultados exitosos. La reducción en el consumo energético respecto a uso de un servidor tradicional con procesador Xeon E3-1200 fue considerable, lográndose en una reducción de hasta 445 watts
Cited by 0Open access
Jianxin Chen, Dawei Ding, Weiyuan Gong et al. · 2024
The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.
Cited by 10
Tariq Jamil · IEEE Potentials · 1995
The author carries out a comparison of CISC (complex instruction set computing) and RISC (reduced instruction set computing). The author discusses what RISC is and its shortcomings. The evolution of CISC and RISC microprocessors is then discussed and prospects for the future are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 28
David A. Patterson, S.D. Seccombe · 1983
Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and testing . . Panelists will discuss the merits of RISCs versus the more traditional instruction sets.
Cited by 1
Guoxiang Guo, Yuanyuan Qi, Minhao Zhu et al. · 2023
The fifth version of the Reduced Instruction Set Computer (RISC-V) is a popular instruction set architecture (ISA) featured for low energy consumption. Currently, a growing number of industrial applications are based on RISC-V platforms, especially Internet of Things (IoT) devices. Those applications pursue low power and just sufficient computing capacity. However, low power consumption shall not be directly regarded as weak in computation. Recent advancement in RISC- V shows the potential for building a computing platform capable of handling tasks requiring considerable computing power. Traditional financial computing platforms are generally based on Complex Instruction Set Computers (CISC), like x86 platforms. As green computing is sweeping, it is meaningful to handle financial computing tasks with less energy consumption. To explore the potential of RISC- V in financial computing, we set up a typical financial computing task - American option implied volatility calculation, and examine the performance and power consumption of x86 and RISC-V platforms. The result shows that the RISC-V CPU is sufficient for some financial computing scenarios considering actual requirements. A heterogeneous computing system composed of x86 and RISC-V platforms could significantly improve energy efficiency.
Cited by 0
Naoki Nishimura, Yasuhiro Awatsuji, Toshihiro Kubota · Applied Optics · 2003
The authors have analysed and evaluated a two-dimensional instruction set of parallel operation based on optical array logic (OAL), which is a digital optical computing paradigm, to clarify efficient composition of an optical computing system based on OAL. To evaluate parallel operation based on OAL, the author have introduced new indices and evaluated a logical instruction set of various parallel operations with the indices, so that a guideline for composing a simple and efficient OAL computing system is clarified. Also, the authors have proposed the reduced operation kernel set correlation technique to perform parallel operations more efficiently by a simple OAL computing system. It has been clarified that the technique can reduce the required hardware necessary for an OAL computing system for efficient general-purpose processing.
Cited by 7
H. R. Archana, Tasneem Sanjana, H T Bhavana et al. · 2021
Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.
Cited by 10
K. Jakub · Open Publication Harvester of National Academy of Sciences of Ukraine · 2017
Machine-code decompilation (i.e. reverse program compilation) is a process often used in reverse engineering. Its task is to transform a platform-specific executable file into a high-level language representation, which is usually the C language. In present, we can find several such tools that support different target architectures (e.g. Intel x86, MIPS, ARM). These architectures can be classified either as RISC (reduced instruction set computing) or CISC (complex instruction set computing). However, none of the existing decompilers support another major architecture type – VLIW (very long instruction word). In this paper, we briefly describe the VLIW architecture together with its unique features and we present several novel approaches how to handle these VLIW-specific features in the decompilation process. We focus on handling of instruction lengths, instruction bundling, and data hazards.
Cited by 0
T. J. Slegel, R. M. Averill, M. A. Check et al. · IEEE Micro · 1999
The IBM S/390 G5 microprocessor in IBM's newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5's level of performance-for example, achieving a very high frequency given the complexity of the architecture.
Cited by 348
Lifu Deng · Applied and Computational Engineering · 2024
The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.
Cited by 2Open access
Cory Merkel, Raqibul Hasan, Nicholas Soures et al. · Computer · 2016
Neuromemristive systems (NMSs) are gaining traction as an alternative to conventional CMOS-based von Neumann systems because of their greater energy and area efficiency. A proposed NMS accelerator for machine-learning tasks reduced power dissipation by five orders of magnitude, relative to a multicore reduced-instruction set computing processor.
Cited by 37
C Sri Vardhan, Giorgio Israel, M. Mohamed Asan Basiri · 2023
Performance is an indispensable factor in processes related to computer architecture. Data Level Parallelism (DLP) is useful to operate on multiple data streams under a single instruction multiple data (SIMD) instructions for improving the performance of the operations on the data. It has a great scope in computing huge chunks of data in an accelerated time, thus finding its applications in scientific calculators, big data processors, and fast computing applications. In this paper, we have proposed an instruction set architecture (ISA) in reduced instruction set computing (RISC)-V using GEM5 that provides faster computational results than the conventional instruction set. Karatsuba algorithm for the $64 \times 64$ bit multiplication can be carried out in several ways including thirty-two $16 \times 8$ bit multiplications, sixty-four $8 \times 8$ bit multiplications, sixteen $32 \times 8$ bit multiplications, and so on. When all the above computations are executed together there is a decrease of 71.55% latency with the proposed implementation in comparison to the conventional implementation. The latency of eight 8-bit additions is decreased by 22.31%, four $8\times 8$ multiplications is decreased by 11.34% and for one $8 \times 8$ bit multiplication and six 8 bit additions, latency is reduced by 19.98%.
Cited by 6
Devyani Gera, Mehul Garg · IOSR Journal of Computer Engineering · 2014
This paper highlights the designingof data and control path of a non-pipelined LC3 microcontroller with a 16 bit Reduced instruction set. The designing was done using a Hardware Descriptive Language (HDL) System Verilog on the platform Questasim Simulator. We have demonstrated the use of this RISC microcontroller using basic ALU operations-ADD, AND & NOT, and a memory operation-Load Effective Address (LEA).The 16 bit reduced instruction used in the designing has been chosensuch that it's computing ends in exactly 5 clock cycles.
Cited by 2Open access