Dean M. Tullsen, Susan J. Eggers, Henry M. Levy · 1995
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited their ability to utilize the resources of a wide-issue processor. Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multithreading. We evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them. We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding conventional multiprocessors with similar execution resources.While simultaneous multithreading has excellent potential to increase processor utilization, it can add substantial complexity to the design. We examine many of these complexities and evaluate alternative organizations in the design space.
Cited by 1,396Open access
Mario Nemirovsky, Dean M. Tullsen · Synthesis lectures on computer architecture · 2013
Cited by 1
Jennifer M. Jayme · 2009
Different Simultaneous Multithreading (SMT) architectures have been proposed and implemented in the industry. Though, as powerful as it sounds over a superscalar processor, design issues are not rare. Addressing a certain problem can be done in hardware or in software; depending on what SMT architecture will you apply it to. Two papers are presented here. The first one, implemented in hardware a solution for wasted resources, heterogeneously clustered SMT architecture. The Heterogeneously Distributed SMT (hdSMT) architecture maximizes the hardware budget by taking into account the heterogeneity of applications. The second paper proposed an Implicitly-Multithreaded (IMT) processor utilizing SMT’s support for multithreading by executing speculative threads. It relied mostly on the compiler to select suitable thread spawning points and orchestrate interthread register communication. I.
Cited by 0
Daniel Ortiz-arroyo, Ben Lee · 2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomplish this, threads are generated dynamically from a predictable flow of control and then executed speculatively. Data obtained during the single context nonspeculative execution phase of DSMT is used as a hint to speculate the posterior behavior of multiple threads. DSMT employs simple mechanisms based on state bits that keep track of inter-thread dependencies in registers and memory, synchronize thread execution, and control recovery from misspeculation. Moreover, DSMT utilizes a novel greedy policy for choosing those sections of code which provide the highest performance based on their past execution history. The DSMT architecture was simulated with a new cycle-accurate, execution-driven simulator. Our simulation results show that DSMT has very good potential to improve SMT performance, even when only a single program is available. However, we found that dynamic thread behavior together with frequent misspeculation may also produce diminishing returns in performance. Therefore, the challenge is to maximize the amount of thread-level parallelism that DSMT is capable of exploiting and at the same time reduce the frequency of misspeculations.
Cited by 0
Heiko Oehring, Ulrich Sigmund, Theo Ungerer · 2007
This paper explores microarchitecture models for a simultaneous multithreaded processor with multimedia enhancements. We start with a wide-issue superscalar processor, enhance it by the simultaneous multithreading technique, by multimedia units, and by an additional on-chip RAM storage. Our workload is a multithreaded MPEG-2 video decompression algorithm that extensively uses multimedia units. The simulations showed that a single-threaded, 8-issue maximum processor (assuming an abundance of resources) reaches an IPC (instructions per cycle) count of only 1.60, while an 8-threaded 8-issue processor is able to reach an IPC of 6.07. A more realistic processor model reaches an IPC of 1.27 in the single-threaded 8-issue vs. 3.21 in the 8-threaded 8-issue model. So, the generalizing conclusion is that an 8-threaded 8-issue processor may yield up to threefold performance increase over the single-threaded 8-issue model. Keywords: Simultaneous multithreading, multimedia extension, MPEG-2 video decompression 1 Introduction
Cited by 6
F. N. Eskesen, Ý M. Hack, Ý T. Kimbrel et al. · 2003
Simultaneous multithreading (SMT) is an approach to address the well-known problems of memory accesses increasingly dominating processor execution time and of limited instruction level parallelism. Previous research has explored the benefits and limitations of SMT based on specific processor architectures under a variety of workloads. In this paper, we present a performance analysis of SMT in a PowerPC-based wide superscalar processor architecture under a broad range of workloads, which includes combinations of TPC-C, SPECint and SPECfp. Although some of our results are consistent with previous work, our results also demonstrate some differences and we use these results to explore and identify the primary causes of such differences. This includes an investigation of thread characteristics that work well together in SMT environments, and thread characteristics that do not work well together. 1
Cited by 0
S. Hily, André Seznec · 2002
In this paper, we examine the behavior of three of the best performing branch prediction strategies proposed in the literature while executing simultaneously several threads of instructions. Our simulations show that in a multiprogramming environment, if the sizes of the tables (PHT/BTB) are proportional to the number of active threads, there are very few interactions. With parallel workloads, we could have expected a beneficial sharing effect. In fact, it is very dependent an the branch predictors and in the best case, the gains stay very limited. We also show that, for the three predictors, whether in multiprogramming or in parallel processing, if the sizes of the tables are kept small, conflicts in the BTB induce a significant increase in mispredictions. However, for parallel processing with the gshare scheme, the resulting misprediction ratios for 2 or 4 threads stay below those exhibited by 1 thread. Finally, we study the impact of the addition of one Return Address Stack per context and show that a 12-deep stack per thread is sufficient to enhance greatly the accuracy of branch prediction.
Cited by 37
D.J. Pease, Mohammad Afzal Hossain · 2002
Instruction fetch throughput is one of the most significant performance bottlenecks of a Simultaneous Multithreading Processor. Instruction fetch throughput limits the execution throughput of a Simultaneous Multithreading Processor even when the processor supports a large number of threads. A Trace Cache can improve instruction fetch throughput of a Superscalar Processor. In this dissertation, we have presented a new processor microarchitecture, Topaz, which adds a Trace Cache to a Simultaneous Multithreading Processor. We show that Topaz improves performance of a Simultaneous Multithreading Processor. An improvement of nine to fourteen percent is observed through our simulations. The results are achieved through mathematical analysis and simulation of SPEC2000 benchmark programs on Topaz. Also, in this dissertation, an analytical model of Trace Cache Miss Rates, and Trace Cache instruction fetch performance are presented. The analytical models are used to develop a new tool, Tulip, for fast performance analysis of Simultaneous Multithreading and Super-scalar processors. Implementation, benefits, and applications of Tulip are presented. The new tool is used as a guide for Topaz design and simulation. The actual simulation is carried out using a detailed cycle accurate out-of-order simulator. A new detailed microarchitecture simulator, Topazsim, is also presented in this dissertation.
Cited by 3
Hossain, Mohammad Afzal · 2002
Instruction fetch throughput is one of the most significant performance bottlenecks of a Simultaneous Multithreading Processor. Instruction fetch throughput limits the execution throughput of a Simultaneous Multithreading Processor even when the processor supports a large number of threads. A Trace Cache can improve instruction fetch throughput of a Superscalar Processor. In this dissertation, we have presented a new processor microarchitecture, Topaz , which adds a Trace Cache to a Simultaneous Multithreading Processor. We show that Topaz improves performance of a Simultaneous Multithreading Processor. An improvement of nine to fourteen percent is observed through our simulations. The results are achieved through mathematical analysis and simulation of SPEC2000 benchmark programs on Topaz. Also, in this dissertation, an analytical model of Trace Cache Miss Rates, and Trace Cache instruction fetch performance are presented. The analytical models are used to develop a new tool, Tulip , for fast performance analysis of Simultaneous Multithreading and Super-scalar processors. Implementation, benefits, and applications of Tulip are presented. The new tool is used as a guide for Topaz design and simulation. The actual simulation is carried out using a detailed cycle accurate out-of-order simulator. A new detailed microarchitecture simulator, Topazsim , is also presented in this dissertation.
Cited by 0
Burns, James Steven (author) · University of Southern California Digital Library · 2014
Cited by 0Open access
T.N. Vijaykumar, Irith Pomeranz, Karl Cheng · ACM SIGARCH Computer Architecture News · 2002
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for transient-fault detection, called Simultaneously and Redundantly Threaded (SRT) processors. SRT replicates an application into two communicating threads, one executing ahead of the other. The trailing thread repeats the computation performed by the leading thread, and the values produced by the two threads are compared. In SRT, a leading instruction may commit before the check for faults occurs, relying on the trailing thread to trigger detection. In contrast, SRTR must not allow any leading instruction to commit before checking occurs, since a faulty instruction cannot be undone once the instruction commits.To avoid stalling leading instructions at commit while waiting for their trailing counterparts, SRTR exploits the time between the completion and commit of leading instructions. SRTR compares the leading and trailing values as soon as the trailing instruction completes, typically before the leading instruction reaches the commit point. To avoid increasing the bandwidth demand on the register file for checking register values, SRTR uses the register value queue (RVQ) to hold register values for checking. To reduce the bandwidth pressure on the RVQ itself, SRTR employs dependence-based checking elision (DBCE). By reasoning that faults propagate through dependent instructions, DBCE exploits register (true) dependence chains so that only the last instruction in a chain uses the RVQ, and has the leading and trailing values checked. SRTR performs within 1% and 7% of SRT for SPEC95 integer and floating-point programs, respectively: While SRTR without DBCE incurs about 18% performance loss when the number of RVQ ports is reduced from four (which is performance-equivalent to an unlimited number) to two ports, with DBCE, a two-ported RVQ performs within 2% of a four-ported RVQ.
Cited by 261
Steven K. Reinhardt, Shubhendu S. Mukherjee · 2000
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardware faults. Most commercial fault-tolerant computers use fully replicated hardware components to detect microprocessor faults. The components are lockstepped (cycle-by-cycle synchronized) to ensure that, in each cycle, they perform the same operation on the same inputs, producing the same outputs in the absence of faults. Unfortunately, for a given hardware budget, full replication reduces performance by statically partitioning resources among redundant operations.We demonstrate that a Simultaneous and Redundantly Threaded (SRT) processor—derived from a Simultaneous Multithreaded (SMT) processor—provides transient fault coverage with significantly higher performance. An SRT processor provides transient fault coverage by running identical copies of the same program simultaneously as independent threads. An SRT processor provides higher performance because it dynamically schedules its hardware resources among the redundant copies. However, dynamic scheduling makes it difficult to implement lockstepping, because corresponding instructions from redundant threads may not execute in the same cycle or in the same order.This paper makes four contributions to the design of SRT processors. First, we introduce the concept of the sphere of replication, which abstracts both the physical redundancy of a lockstepped system and the logical redundancy of an SRT processor. This framework aids in identifying the scope of fault coverage and the input and output values requiring special handling. Second, we identify two viable spheres of replication in an SRT processor, and show that one of them provides fault detection while checking only committed stores and uncached loads. Third, we identify the need for consistent replication of load values, and propose and evaluate two new mechanisms for satisfying this requirement. Finally, we propose and evaluate two mechanisms—slack fetch and branch outcome queue—that enhance the performance of an SRT processor by allowing one thread to prefetch cache misses and branch results for the other thread. Our results with 11 SPEC95 benchmarks show that an SRT processor can outperform an equivalently sized, on-chip, hardware-replicated solution by 16% on average, with a maximum benefit of up to 29%.
Cited by 618
Jack Lo, Susan J. Eggers, Henry M. Levy et al. · International Journal of Parallel Programming · 1999
Cited by 2
Acosta Ojeda, Carmelo Alexis, Falcón Samper, Ayose Jesús, Ramírez Bellido, Alejandro et al. · RECERCAT (Consorci de Serveis Universitaris de Catalunya)
Different applications may exhibit radically different behaviors and thus have very different requirements in terms of hardware support. In simultaneous multithreading (SMT) architectures, the hardware is shared among multiple running applications in order to better profit from it. However, current architectures are designed for the common case, and try to satisfy a number of different application classes with a single design. That is, current designs are usually overdesigned for most cases, obtaining high performance, but wasting a lot of resources to do so. In this paper we present an alternative SMT architecture, the heterogeneously distributed SMT (hdSMT). Our architecture is based in a novel combination of SMT and clustering techniques in a heterogeneity-aware fashion. The hardware is designed to match the heterogeneous application behavior with the statically and heterogeneously partitioned resources. Such a design is aimed for minimizing the amount of resources wasted to achieve a given performance rate. On top of our statically partitioned architecture, we propose a heuristic policy to map threads to clusters so that each cluster matches the characteristics of the running threads and overall hardware usage is optimized. We compare our hdSMT architecture with a monolithic SMT processor, where all threads compete for the same resources, and with a homogeneous clustered SMT, where resources are statically and equally partitioned across clusters. Our results show that hdSMT architectures obtain an average improvement of 13% and 14% in optimizing performance per area over monolithic SMT and homogeneously clustered SMT respectively.
Cited by 0Open access
T.N. Vijaykumar, Irith Pomeranz, Karl Cheng · 2003
We propose a scheme for transient-fault recovery called Simultaneously, and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for transient-fault detection, called Simultaneously and Redundantly Threaded (SRT) processors. SRT replicates an application into two communicating threads, one executing ahead of the other. The trailing thread repeats the computation performed by the leading thread, and the values produced by the two threads are compared. In SRT a leading instruction may commit before the check for faults occurs, relying on the trailing thread to trigger detection. In contrast, SRTR must not allow any leading instruction to commit before checking occurs, since a faulty instruction cannot be undone once the instruction commits. To avoid stalling leading instructions at commit while waiting for their trailing counterparts, SRTR exploits the time between the completion and commit of leading instructions. SRTR compares the leading and trailing values as soon as the trailing instruction completes, typically before the leading instruction reaches the commit point. To avoid increasing the bandwidth demand on the register file for checking register values, SRTR uses the register value queue (RVQ) to hold register values for checking. To reduce the bandwidth pressure on the RVQ itself SRTR employs dependence-based checking elision (DBCE). By reasoning that faults propagate through dependent instructions, DBCE exploits register (true) dependence chains so that only the last instruction in a chain uses the RVQ, and has the leading and trailing values checked. SRTR performs within 1% and 7% of SRT for SPEC95 integer and floating-point programs, respectively. While SRTR without DBCE incurs about 18% performance loss when the number of RVQ ports is reduced from four (which is performance-equivalent to an unlimited number) to two ports, with DBCE, a two-ported RVQ performs within 2% of a four-ported RVQ.
Cited by 152
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy · 2002
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multi-threading. We evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them. We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding conventional multiprocessors with similar execution resources. While simultaneous multithreading has excellent potential to increase processor utilization, it can add substantial complexity to the design. We examine many of these complexities and evaluate alternative organizations in the design space.
Cited by 563
Carmelo Acosta, Ayose Falcón, A. Ramirez et al. · UPCommons institutional repository (Universitat Politècnica de Catalunya) · 2005
Different applications may exhibit radically different behaviors and thus have very different requirements in terms of hardware support. In simultaneous multithreading (SMT) architectures, the hardware is shared among multiple running applications in order to better profit from it. However, current architectures are designed for the common case, and try to satisfy a number of different application classes with a single design. That is, current designs are usually overdesigned for most cases, obtaining high performance, but wasting a lot of resources to do so. In this paper we present an alternative SMT architecture, the heterogeneously distributed SMT (hdSMT). Our architecture is based in a novel combination of SMT and clustering techniques in a heterogeneity-aware fashion. The hardware is designed to match the heterogeneous application behavior with the statically and heterogeneously partitioned resources. Such a design is aimed for minimizing the amount of resources wasted to achieve a given performance rate. On top of our statically partitioned architecture, we propose a heuristic policy to map threads to clusters so that each cluster matches the characteristics of the running threads and overall hardware usage is optimized. We compare our hdSMT architecture with a monolithic SMT processor, where all threads compete for the same resources, and with a homogeneous clustered SMT, where resources are statically and equally partitioned across clusters. Our results show that hdSMT architectures obtain an average improvement of 13% and 14% in optimizing performance per area over monolithic SMT and homogeneously clustered SMT respectively.
Cited by 3Open access
Allan Snavely, Dean M. Tullsen, Multithreading Processor · 2000
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coschedule This paper demonstrates that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without anyadvance knowledge of a workload's characteristics, using sampling to identify jobs which run well together. We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about variou...
Cited by 0
A. Gray, Joachim Hein, Martyn Plummer et al. · 2006
The use of Simultaneous Multithreading (SMT) on HPCx is investigated to determine if any performance improvement is obtainable for user applications. Various codes are benchmarked with and without the use of SMT. SMT is seen to boost the performance, at low and moderate processor counts, of the H2MOL application and the classical molecular dynamics codes NAMD, MDcask and DL POLY, with up to a factor of 1.4 improvement observed. No performance improvement is seen when using SMT with the materials science CASTEP code, the ScaLAPACK eigensolver routines or the STREAMS memory bandwidth benchmark. This is a Technical Report from the HPCx Consortium c ○ HPCx UoE Ltd 2005 Neither HPCx UoE Ltd nor its members separately accept any responsibility for loss or damage from the use of information contained in any of their reports or in any communication In general, the execution of real applications results in the functional units of the processor
Cited by 2
Manoj Gupta, Fermín Sánchez Carracedo, Josep Llosa · IEEE Transactions on Computers · 2009
Simultaneous MultiThreading (SMT) is a well-known technique that improves resource utilization by exploiting thread-level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures, which is contrary to the VLIW philosophy of hardware simplicity. In this paper, we propose Cluster-level Simultaneous MultiThreading (CSMT) to allow some degree of SMT in clustered VLIW processors with low hardware cost and complexity. CSMT considers the set of operations that execute simultaneously in a given cluster as the assignment unit. To minimize cluster conflicts between threads, a very simple hardware-based cluster renaming mechanism is proposed. The hardware required to implement CSMT is cheap, realistic, and practical for a clustered VLIW processor. An analysis of the hardware required to implement CSMT shows that it is quite scalable, with up to eight threads easily supported at low hardware cost. The experimental results show that CSMT significantly improves performance when compared with other multithreading approaches suited for VLIW. For instance, with four threads, CSMT shows an average speedup of 110 percent over a single-thread VLIW architecture and 40 percent over Interleaved MultiThreading (IMT). In some cases, speedup can be as high as 225 percent over single-thread architecture and 84 percent over IMT.
Cited by 3