François Gagnon, N. Batani, Thu-Lan Dam · 2002
New fully digital hardware designs for soft-decision threshold decoders are introduced to significantly reduce the complexity and increase the coding gain as compared to previously proposed architectures. These designs are useful for high-rate self-orthogonal convolutional codes with a long constraint length. The study case considered in this paper is for a rate 23/24, constraint length 4056 code used in a typical microwave digital radio. The new decoder architecture provides a four-fold decrease in complexity and an additional 0.3 dB coding gain as compared to previous designs. The simplification of the decoding architectures is possible through the use of three techniques: a different processing of feedback, the separation of information bit and reliability bit processing and the use of partial reencoding.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Baliga, Naveen Bantwal · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2021
The IEEE 802.11a protocol is part of the IEEE 802 protocols for implementing WLAN Wi- Fi computer communications in various frequencies. These protocols find applications worldwide, covering a wide range of devices like mobile phones, computers, laptops, household appliances, etc. Since wireless communication is being used, data that is transmitted is susceptible to noise. As a means to recover from noise, the data transmitted is encoded using convolutional encoding and correspondingly decoded on the receiver side. The decoder used is the Viterbi decoder, in the PHY layer of the protocol. This thesis investigates soft-decision Viterbi decoder implementations that meet the requirements of the IEEE 802.11a protocol. It aims to implement a rate-flexible design as a coarse grain re-configurable architecture using the SiLago framework. SiLago is a modular approach towards ASIC design. Components are designed as hardened blocks, which means they are synthesised and pre-verified. Each block is also abuttable like LEGO blocks, which allows users to connect compatible blocks and make designs specific to their requirements, while getting performance similar to that of traditional ASICs. This approach significantly reduces the design costs, as verification is a one-time task. The thesis discusses the strongly connected trellis Viterbi decoding algorithm and proposes a design for a soft decision Viterbi decoder. The proposed design meets the throughput requirements of the communication protocol and it can be reconfigured to work for 45 different code rates, with programmable soft decision width and parallelism. The algorithm used is compared against MATLAB for its BER performance. Results from RTL simulations, advantages and disadvantages of the proposed design are discussed. Recommendations for future improvements are also made.
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Unknown · University of Southern California Digital Library · 2012
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Stefan Scholl, Syed Kamran Haider, Norbert Wehn · 2016
Soft decision decoding for Reed-Solomon codes has been proven to provide large coding gains in comparison to conventional hard decision decoding. Out of the numerous soft decoding algorithms, information set decoding has turned out to be an efficient approach, if coding gains larger than 0.5 dB are desired for the widely used RS(255,239) code. In this paper we investigate new hardware implementations for information set decoding for moderate throughput applications with the aim to reduce the decoder area. We propose new efficient architectures for the key components, i.e. LLR sorting, Gaussian elimination and parity check matrix storage. The decoder requires 4950 lookup tables and 5340 flipflops on a Virtex 5 FPGA to achieve 0.7 dB gain over hard decision decoding. This is approximately 3 to 20 times less FPGA resources than other state-of-the-art architectures with similar coding gain at the expense of throughput. The decoder throughput fulfils the requirement for many applications with moderate demands, like DAB or DRM.
Cited by 2
Xinmiao Zhang, Jiangli Zhu · 2010
Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Among ASD algorithms, the low-complexity Chase (LCC) algorithm can achieve better performance-complexity tradeoff. This algorithm tests 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> vectors, and larger η leads to higher coding gain. One major step of the LCC decoding is the interpolation, and its latency grows exponentially with η. To reduce the latency, multiple interpolators can be used to test the vectors in parallel. However, they lead to large area requirement. This paper proposes to interpolate over the points in the test vectors in a different order. By making use of the properties of the interpolation points in the rearranged order, novel schemes are developed to simplify and share computations among the interpolators. From complexity analysis, the proposed interpolation scheme can achieve higher speed and reduce the area requirement by 30% for a (255, 239) RS code with η = 5 when 4-parallel interpolation is employed. The proposed interpolation architecture is incorporated into the LCC decoder and further optimizations are carried out. For the same RS code, the proposed decoder can achieve 16% speedup with 11% less area than the previous design.
Cited by 12
Tanaka, Hatsukazu, 田中, 初一, タナカ, ハツカズ et al. · Kobe University Repository Kernel (Kobe University) · 1982
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김창현 · Open Access System for Information Sharing (Pohang University of Science and Technology) · 2022
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Hayato Goto, Hironori Uchikawa · Physical Review A · 2014
A soft-decision decoder for quantum erasure errors with standard depolarizing errors is proposed for concatenated Calderbank-Shor-Steane codes. This decoding is computationally efficient as long as the block size of each concatenation level is sufficiently small. The numerical simulation with a specific quantum code called the ${C}_{4}/{C}_{6}$ code shows that this decoder can achieve almost optimal performance and the so-called hashing bound for the erasure and depolarizing error model. Since probabilistic-gate errors can be regarded as erasure errors, this decoder is useful for fault-tolerant quantum computation with probabilistic gates. To demonstrate this, we perform numerical simulation with the ${C}_{4}/{C}_{6}$ code. Consequently, it turns out that the error probability of a logical controlled-not gate with probabilistic physical two-qubit gates is improved by three orders of magnitude by the present decoder compared to a previous hard-decision decoder.
Cited by 4
Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga · Integration · 2011
Cited by 5
S Jeseena, Suby Varghese · 2018
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ijeit · OSF Preprints (OSF Preprints) · 2020
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Adde, Patrick, Christophe Jégo, Raphaël Le Bidan et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2010
International audience
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Aliaa Said Mousa, Mahmoud Fathi Mahmoud, A. I. Taman · 2015
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Tadashi Fujino, Yuki Moritani, Makoto Miyake et al. · 1986
Cited by 7Open access
Qolamreza Nadalinia Charei, H Fazlollahi Aghamalek, S M Razavi et al. · 2013
In this paper, the application of artificial neural networks to improve the efficiency of soft decision in Viterbi decoder is proposed. By adding neural network to the decision block of Viterbi decoders and training in supervisor manner, neural networks will be able to anticipate and handle a wide range of distortion. Using the neural networks soft decision in Viterbi decoder block would reduce the bit error rate (BER) in data transmission for AWGN channels. This method can provide low bit BER for data transmission on channels with low signal to noise ratio (SNR). The results show that the proposed technique can improve the efficiency of decision making in comparison with other methods of decision making (soft, hard and slow), in term of BER.
Cited by 5
Ali Mohammed Kadhim, Wisam Subhi Al-Dayyeni, Majid S. Naghmash · Lecture notes in networks and systems · 2023
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Wieruch, D., Kühling, D., Ibing, A. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 2008
A 64-state soft-decision Viterbi algorithm implementation on a Cell CPU running at 2.8 GHz is presented, which achieves a throughput of 250 MBit/s, 500 MBit/s encoded data, where the 8 SPU cores process different packets in parallel. Evaluations are done using the IEEE 802.11a, WiMAX and DVB code polynomials. The implementation is done in C language using the GNU C compiler. The code uses optimizations like instruction level parallelism, loop unrolling and indepent processor pipelines.
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Sangwook Suh · SMARTech Repository (Georgia Institute of Technology) · 2011
The purpose of this research is to present a low-power wireless communication receiver with an enhanced performance by relieving the system complexity and performance degradation imposed by a quantization process. With an overwhelming demand for more reliable communication systems, the complexity required for modern communication systems has been increased accordingly. A byproduct of this increase in complexity is a commensurate increase in power consumption of the systems. Since the Shannon's era, the main stream of the methodologies for promising the high reliability of communication systems has been based on the principle that the information signals flowing through the system are represented in digits. Consequently, the system itself has been heavily driven to be implemented with digital circuits, which is generally beneficial over analog implementations when digitally stored information is locally accessible, such as in memory systems. However, in communication systems, a receiver does not have a direct access to the originally transmitted information. Since the received signals from a noisy channel are already continuous values with continuous probability distributions, we suggest a mixed-signal system in which the received continuous signals are directly fed into the analog demodulator and the subsequent soft-decision Viterbi decoder without any quantization involved. In this way, we claim that redundant system complexity caused by the quantization process is eliminated, thus gives better power efficiency in wireless communication systems, especially for battery-powered mobile devices. This is also beneficial from a performance perspective, as it takes full advantage of the soft information flowing through the system.
Cited by 2
Chaoyi Zhang, Haiyang Liu, Songlin Ou et al. · Communications in computer and information science · 2017
Cited by 1
Weigang Chen, Zhao Tian, Changcai Han · Electronics · 2023
The soft decision decoding algorithm for cyclic codes, especially the maximum likelihood (ML) decoding algorithm, can obtain significant performance superior to that of algebraic decoding, but the complexity is much higher. To deal with this problem, an improved soft decision decoding algorithm based on a cyclic information set and its efficient implementation architecture are proposed. This algorithm employs the property of the cyclic codes to generate a series of cyclic information sequences by circularly shifting, constructing the cyclic information set. Then, a limited number of candidate information sequences are efficiently generated using an iterative computation method, and the candidate codewords are generated using the very concise encoding method of the cyclic codes. Furthermore, the efficient hardware architecture based on systolic arrays is also proposed to generate candidate information sequences and to select the optimal candidate codewords. An emulation platform is constructed to verify the error correction performance and to determine the optimal decoder parameters. Emulation results indicate that, with appropriate parameter selection, the proposed decoding algorithm can achieve a bit error rate approaching the ML performance while maintaining low complexity.
Cited by 3Open access