Speedup
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About 10,000 papers for “Speedup”
JINR Document Server (Joint Institute for Nuclear Research)
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Unknown · Open MIND · 2012
graph. Darst.
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Jose-Ignacio Agulleiro (124327), José Jesús Fernández (124330) · Figshare · 2015
<p>Both WBP and SIRT have been taken into account. (a) Speedup provided by individual optimizations. Using the basic optimizations we reach a speedup slightly higher than 6x, with SSE instructions we are close to the theoretical 4x, and with two and four threads we can say that the speedup is linear with the number of cores. With eight threads it decreases a little. (b) Accumulated speedup. If we include basic optimizations and SSE instructions, the speedup is around 20x. When using two, four and eight threads, it rises above 40x, 80x and 160x, respectively.</p>
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Fred Wright · University of Pittsburgh Digital Library
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Jianfang Cao (1881379), Yanfei Li (3413285), Yun Tian (411157) · Figshare · 2018
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Nadav Kashtan (265054), Avi E. Mayo (265056), Tomer Kalisky (216741) et al. · Figshare · 2015
<p>(A) Speedup as a function of goal switching times <i>E</i>.\n Speedup is presented for the goal <i>G<sub>1</sub></i>\n with MVG between the nearly modular pair of goals\n <i>G<sub>1</sub></i> and <i>G<sub>2</sub> :\n G<sub>1</sub></i> = {\n [ (−0.4,−1.6,0.7),\n (−0.4,−1,−2.3) ]; [\n (0,0.9,−0.3), (0,0.7,1.2) ] },\n <i>G<sub>2</sub></i> = {\n [ (2,−1.9,1.7),\n (2.9,−0.3,−3.6) ];[\n (0.3,0.3,0.3), (0.4,0.6,−0.1) ] }, . High speedup <i>S</i> is found for a\n wide range of goal switching times. (B) Speedup under MVG is greater\n the harder the goal (the more time it takes to solve the goal in FG\n evolution starting from random initial conditions). The Speedup\n <i>S = T<sub>FG</sub>\n / T<sub>MVG</sub></i> as a function of goal complexity,\n defined as the time to solve the goal under fixed goal evolution,\n <i>T<sub>FG</sub></i>. The speedup scales linearly\n with <i>T<sub>FG</sub></i>. Goals are as in (a). and\n <i>E = 10/r</i>.</p>
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Alan Fern · 2007
Speedup learning is a branch of machine learning that studies learning mechanisms for speeding up problem solvers based on problem solving experience. The input to a speedup learner typically consists of observations of prior problem-solving experience, which may include traces of the problem solver’s operations and/or solutions to solved problems. The output is knowledge that the problem solver can exploit to find solutions more quickly than before learning without seriously effecting solution quality. The most distinctive feature of speedup learning, compared to most branches of machine learning, is that the learned knowledge does not provide the problem solver with the ability to solve new problem instances. Rather, the learned knowledge is intended solely to facilitate faster solution times compared to the solver without the knowledge. Motivation and Background Much of the work in computer science and especially artificial intelligence aims at developing practically efficient problem solvers for combinatorially
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Alan Fern · Encyclopedia of Machine Learning and Data Mining · 2017
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Yue Hu, Weiqin Tong, Xiaoli Zhi et al. · 2010
In the optimizing work of parallel program, especially in the realm of massively parallel computing, the parallel computing time and space must be concurrently carefully considered to cut down the computing time as much as possible, because lots of poor parallel space strategies would impact negative effects on computing time. Although, sometimes we have no choice but to sacrifice the space for the time's further diminishing. What relationship should the computing time and space to keep and how are they going on are two problems, which deciding our optimizing direction directly and must be clear in parallel optimizing. This paper proposes a space theory, named as space speedup, to denote the scalability of memory requirement, and discusses the relationship of time speedup and space speedup, through which the speedups' guidance capacity in optimizing parallel codes are given.
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Rong Ge, Kirk W. Cameron · 2007
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware clusters can conserve significant energy (>30%) with minimal performance loss (<1%) running parallel scientific workloads. Nonetheless, such savings are typically achieved using a priori knowledge of application performance. Accurate prediction of parallel power consumption and performance is an open problem. However, such techniques would improve our understanding of power-aware cluster tradeoffs and enable identification of system configurations optimized for performance and power ("sweet spots"). Speedup models are powerful analytical tools for evaluating and predicting the performance of parallel applications. Unfortunately, existing speedup models do not quantify parallel overhead for simplicity. Consequently, these models are incapable of accurately accounting for performance and power. We propose power-aware speedup to model and predict the scaled execution time of power-aware clusters. The new model accounts for parallel overhead and predicts (within 7%) the power-aware performance and energy-delay products for various system configurations (i.e. processor counts and frequencies) on NAS parallel benchmark codes.
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England, R., Yanev, S., Boyanov, K. et al. · Research Output (Edinburgh Napier University) · 1996
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Paul Richmond (352031), Lars Buesing (337191), Michele Giugliano (227795) et al. · Figshare · 2015
<p>Figure shows the relative performance improvement of our GPU model with\n respect to a similar Python implementation using numpy's BLAS\n implementation. Relative performance refers to the percentage increase\n in performance by considering the absolute timings of the two\n implementations over an entire simulation. The horizontal axis indicates\n <b>Ind_total</b>, that is the total number of independent\n trials which in this case represents independent animats (rather than\n animats in different configurations). A: Represents the case for our\n model without lateral connections. B: Represents a case with lateral\n connections which is the same however it includes an additional code\n execution to perform simulation of the lateral spike propagation.</p>
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Jonathan W. Stone (107593), Samuel Bleckley (107590), Sean Lavelle (677485) et al. · Figshare · 2015
<p>Speed up is the ratio of real computation time in serial to real computation time in parallel. The computational input and parameters and color legend are the same as for figs. <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0117217#pone.0117217.g007" target="_blank">7</a> and <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0117217#pone.0117217.g008" target="_blank">8</a>.</p>
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Jiaheng Lu, Yuxing Chen, Herodotos Herodotou et al. · Proceedings of the VLDB Endowment · 2019
Database and big data analytics systems such as Hadoop and Spark have a large number of configuration parameters that control memory distribution, I/O optimization, parallelism, and compression. Improper parameter settings can cause significant performance degradation and stability issues. However, regular users and even expert administrators struggle to understand and tune them to achieve good performance. In this tutorial, we review existing approaches on automatic parameter tuning for databases, Hadoop, and Spark, which we classify into six categories: rule-based, cost modeling, simulation-based, experiment-driven, machine learning, and adaptive tuning. We describe the foundations of different automatic parameter tuning algorithms and present pros and cons of each approach. We also highlight real-world applications and systems, and identify research challenges for handling cloud services, resource heterogeneity, and real-time analytics.
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Kerridge, Jon M., England, R., Yanev, S. et al. · Edinburgh Napier Research Repository (Edinburgh Napier University) · 1996
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Touati, Sid, Worms, Julien, Briais, Sébastien · HAL (Le Centre pour la Communication Scientifique Directe) · 2010
A software is included with the document: the software implements the speedup-test protocole.
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Moritz Hoffmann (6411821), Christoph Fröhner (6411824), Frank Noé (364855) · Figshare · 2019
<p>Parallel speedup and efficiency of the benchmark system of Sec. Performance as a function of the number of cores using the machine described in <a href="http://www.ploscompbiol.org/article/info:doi/10.1371/journal.pcbi.1006830#pcbi.1006830.g003" target="_blank">Fig 3</a>. <b>(a)</b> Speedup with different numbers of cores compared to one core. Optimally one would like to have a speedup that behaves like the identity (black dashed line). <b>(b)</b> Efficiency is the speedup divided by the number of threads, i.e., how efficiently the available cores were used.</p>
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Poul E. Heegaard · 1997
This presentation gives a brief survey of speedup techniques for discrete event simulation where the quantity of interest depends on rare events to occur. Both rare event simulation approaches like RESTART/splitting and importance sampling and other complementary techniques are described. A list of key references to the various techniques are included. As a pragmatic or engineering approach, it is recommended that the different techniques are combined whenever possible instead of seeking the universal optimal technique for all applications. An example of such an approach is included. 1 INTRODUCTION The focus of this tutorial is discrete event simulation where the quantity of interests depends on rare events to occur, see figure 1(a). A survey of speedup simulation techniques in a broader sense than the &quot;Rare Event Simulation&quot; is given. Speedup simulation is here defined as &quot;any technique which increases the efficiency of a simulation experiment&quot;. Roughly speaking, two approaches appl...
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Bulletin of Miscellaneous Information (Royal Gardens Kew)
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Belforte, Piero · 2018
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